Perhaps a magic information fairy pointed him to an Intel Technology Journal Article
"TERA-SCALE MEMORY CHALLENGES AND SOLUTIONS"
And this corresponding patent:
"Systems, methods, and apparatuses for hybrid memory"
Sounds similar to what Huawei/Altera are doing and what I expect other comms and server OEMs will try out over the next year or so.
Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU.
stacking memory on the CPU makes a lot of sense for any lower-power chip - after all, it's pretty routine in phones. stacking not only gives a performance boost, but saves some power. probably hard to do with a bigger/hotter chip, though.
10W is certainly workable for a tablet, as long as it can race to sleep, low leakage, etc.
I just wish AMD would grow some balls and produce, for instance, an APU with stacked dram so you could tile a bunch of them onto a board. whatever happened to the idea of scalable multiprocessor systems anyway? (with builtin scalable GPU for free!)
It's still a little rumor-like to me. I also saw Anand report it as embedded DRAM as if on-chip, but if it is off- chip, would they use TSV for the speed? Isn't the normal course to make it on-chip SRAM?
As we unveil EE Timesí 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.