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green_is_now
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re: Enhancing the efficiency of photovoltaic systems
green_is_now   1/18/2013 5:23:40 PM
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Microsmi makes vry lo pwer FPGA device. Misleading is the use of 1t,2nd,srd for efficiencyimprovements the are all seperate and inependent issues. MPPT input power otimization. PWM, how any MPPT, PFC, PFM or PWM circuit works, it s the basis of all modern power conversion. PFC = current propotionl to voltage... over fundamental period. All must be used together to maxamize efficiency.

Some Guy
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re: Enhancing the efficiency of photovoltaic systems
Some Guy   11/16/2012 10:32:26 PM
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At a systems level, if you have any electrical storage in the system, you are best off to connect the panels and the batteries by DC, not AC. That typically results in 10% more energy available when you invert the AC out of the storage. (1. Eliminates a conversion: DC -DC - AC instead of DC - AC - DC - AC, and 2. higher end-to-end efficiency)

jadwin79
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re: Enhancing the efficiency of photovoltaic systems
jadwin79   11/16/2012 4:29:05 PM
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If by "prevalent" you mean installed capacity, then wind far outstrips solar. Latest numbers I saw were 238 GW for wind, 67 GW for solar. You also mention solar efficiency of 19% (that is a typical number for panels themselves) and then say we need 95% to "maximize use of harvested solar energy". I think you probably meant to say that just the inverter efficiency should target 95% since basic physics limits existing Si panel efficiency to about half that.



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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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