It's always been a fundamental question, in a multi-layered memory, with the peripheral portion taking up more and more area, perhaps even initially exceeding the array area, doesn't the cost/bit reduction from additional layers quickly reach its limit, making it questionable to say it extends scalability?
NAND is commercialized, so any talk at the conference is only leading to its demise. However, it is so entrenched, it doesn't need growth, and its demise won't happen overnight. On the other hand, exposing faults of MRAM or FRAM could severely limit their ability to grow their markets, right now.
i don't know perhaps the same reason antiquated limited write NAND Flash is still being researched
and talked about at research conferences?
and OC i don't recall it being said saying anything about it being "well-researched" only that its now a commercial product in a form people might use generally.
just because a produce is commercialized doesn't stop it being researched to bring improvements,NAND Flash proves that.
and by that i mean everyone knows antiquated "limited write" NAND Flash SSDs are reaching their limits already and wont go much past their current speeds , its time to transition and everyone put cash into Mram and move move over until the other stuffs finally out the Lab and on the shelfs for real.
and not to take focus away from MRAM above, theres also the news that samsung just made a 64GB embedded multimedia card (eMMC) using [10nm]-class process technology to also consider http://www.digitimes.com/news/a20121116PR206.html
its just a comment you understand but theres something very wrong here, it seems all these are test chips fresh out the lab, now thats good.
don't get me wrong, but people are fed up now always hearing whats perpetually always in the lad or test chip, and for no other reason than its here "last year’s ISSCC is 64Mb for ReRAM and 8Gb for PRAM"
theres also mention of smaller future processes and how thats good 16nm,22nm,24nm etc
however where are the commercial products Today, and why didn't F RAM get a mention here ?
or Especially Mram gets only "making steady progress towards product introductions..." when
after talking with everspin on the phone directly states something far better , it's commercially available "NOW", "The ST-MRAM shown today is built on a standard 90nm process, and from that you get a 64Mb chip that is pin compatible with a DDR3 DRAM."
"Current DDR3 controllers, if they follow the spec fully, should be able to work with ST-MRAM."
"Looking forward a bit, if you can get 64Mb chips out of a 90nm process, think about what happens when you move to a modern process. Process"
and he finishes with best of all
"Impending shrinks mean ST-MRAM has a pretty good outlook. Once this technology goes mainstream it will change things, count on it.S|A"
so all told, finally we get this new (well old given Freescale commercialized oddball versions of this 2004 before passing it to everspin) fast as current Dram packages, in a cheap and generic 90nm process with lots of very quick progression to something even better Now, today,in stock,commercially,and so retail real soon now (in the real meaning of the end user word...)
like i said only wanted to make a comment, sorry for the tangent but you and everyone should be screaming this from all the front pages so people buy...
@resistion, here's a link to the advanced program:
I'll see if I can get access for the press materials for you folks, which has some more detail but is gated right now.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.