At 10 nm, probably half of the layers are double patterning, the other half is single-patterned, and only the fin layer is quadruple patterned. So this is maybe 50% extra cost, but the density is improved maybe 4X, so the cost per transistor is still reduced, just not as much.
I think that IDMs like Intel and Samsung still have an edge over the foundries due to their better integrated process technologies. I don't know that being 30% more expensive for an applications processor is such a big deal for Intel in the grand scheme of things either as long as the performance (both speed and low power) is there. The foundries will catch up eventually but it will take several more years.
The fin pitch is 60 nm which is sublithographic, so requires double patterning. It's just one layer, but look at the gate and isolation pitches they are around 90 nm, which is also what foundry 28 nm offers. It's hard to argue that for this particular comparison, Intel has a cheaper process. Maybe they got performance and yield (which is another major cost factor).
Cost numbers come from our competitive analysis group . Has a program that calculated cost from die size, wafer, test and packaging cost.
Valley view die sizes are still all under NDA. But we know there are two version 2 or 4 cores and parts and the parts use ivy brige 2C graphic unit (~30mm^2 silicon area). The Atom cores will be about .8X smaller in 22 vs 32nm. Thus die size are is range 60-80mm^2
But I spoke to someone in Intel Procurement Group about why they are taping out LTE and RF mobile chips at TSMC 28nm. Intel guy said Intel's advanced internal nodes manufacturing (22 and 14nm) was not cost effective with foundry.
Maybe this has to do with opportunity cost
"Implication for Intel's first 22nm Valley view (Atom SOC) will have somewhere in the neighborhood 30-40% higher cost than equal parts from Qualcomm (snapdragon) or nVidia (Tegra 4) fabricated parts in foundry 28LP or 28HPM"
I am curious how you came up with this number 30 to 40%
What's Valley View die size?
BRCM just reiterated NVDA's dim projection that Moore's law is slowing down significantly for the foundries and TI probably exited the mobile business for the very same reason.
GloFlo breaking even in 2015?
Disclosure : heavily invested in arms - I mean arms supplied by KLAC, LRCX & NVLS (double patterning) and ASML
I thought Peter's article about Gloflo trying to break even in 2015 is pretty sobering.
It raises the question of how good are TSMC's 28nm margin during the first 12 months - TSMC has the advantage to make huge profits off legacy technology - Gloflo does not.
In the past Intel (and also AMD) used depreciated equipment to manufacture NOR flash -
perhaps 32nm Medfield is using similar approach being fabbed with more or less depreciated 45nm equipment.
Paul O. made also some comments about foundry bizz during Bernstein presentation -
no intention to compete with TSMC rather focusing on "value" deals without compromising the core business.
I look at it like this.
You can chip 28nm SOC with integrated application/base band processor now
or you can ship same transistor density chips in Intel's 22nm SOC in 2014 but only application processor
It should be clear why Intel is loosing in mobile and CEO is out.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.