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re: Intel's 22-nm tri-gate SoC, how low can you leak?
WiLess   12/12/2012 1:10:57 AM
TSMC has an infrastructure and process to enable IP houses to develop analog, memory and other process-specific IP. That way anyone who uses the new process can choose from many offering. That's my understanding why Intel's mobile offerings are so poor-featured compared ARM-based developed by Qualcomm, Samsung and Nvidia. Tri-gate process is a great improvement and the step in the right direction to enable mobile market, but I am not sure if this is sufficient alone. Even if Intel opens its fab to others today, it still has a lot to catch up with the way other fabs are supporting their customers. Thanks for the interesting article!

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re: Intel's 22-nm tri-gate SoC, how low can you leak?
danny1024   12/11/2012 11:15:47 PM
Everyone who plays/played the "Master of Orion" or the "Civilization" series of global/galactic strategy games knows that "raping the tech tree" is the key to victory. I can't see how that's any different for the semiconductor industry and the process technology tree.

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re: Intel's 22-nm tri-gate SoC, how low can you leak?
resistion   12/11/2012 3:39:37 AM
This looks like (at least) a dual gate oxide SoC, so it's definitely more expensive to make than single gate oxide logic. Triple gate oxide is not unheard of either. The gate layer in this case is therefore already triple patterned for non-lithographic, electrical reasons alone.

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re: Intel's 22-nm tri-gate SoC, how low can you leak?
krisi   12/10/2012 11:40:42 PM
The slide shows leakage getting smaller as the feature size decreases...this can't be true!!!

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re: Intel's 22-nm tri-gate SoC, how low can you leak?
SylvieBarak   12/10/2012 10:52:03 PM
My pleasure. I don't have any information on how this will affect the packaging just yet, but I'll try to find out for you. Glad you enjoyed the article!

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re: Intel's 22-nm tri-gate SoC, how low can you leak?
sranje   12/10/2012 9:58:06 PM
Thank you Sylvie very much ! It would be interesting to hear what will be the impact on IC packaging.... Any information on that? Thanks once again

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