For some time IBM has not invested in leading edge Fabs . So they have a reason to pursue TSV based 3D stacking, partitioning of functions ( SRAM, I/O etc. ). The thermal and stress issues of 3D stacking w/ TSVs are only beginning to be studied and both routing and performance would be affected by these factors.
Integration at the Package level w/o compromising performance too much requires fine - pitch thin film interconnects and soon drilling holes ( TSVs ) in live Si. This is by no means cheap. By not building Fabs of the latest node IBM saves on Capital but their unit cost goes up because of expensive packaging. But they make large and expensive systems so additional part costs get buried.
Companies that sell less than million units of high priced chips ( e,g. FPGA ) are next in line for integration at Package level.
This is not the case for Consumer systems where the massive volume enables at least the leaders to build the latest Fabs and integrate everything ( as in a SoC ) on a single small chip. As some of the leading Fabless companies who have recently dabbled in 3D stacking etc. have found out, cost would be a big deterrent.
So for them its back to the Intel single chip approach ( but built at offshore Foundries )
IBM has been filling B323A in East Fishkill N.Y. for years with tooling for advanced nodes. It seems to have been their plan all along. They are running 22nm and 14nm development in pretty good volumes on the latest immersion tools. I don't understand the reference to " has not invested in a leading edge Fab" for quite some time , there is still room to expand in the current building, and as far as I know, they can support at least the next two nodes there.
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