World major foundries, TSMC, Samsung, GlobalFoundries, and UMC all get on to the Intelís FinFET bandwagon after falling behind Intel. They all plan to introduce FDFinFETs at the 14-nm node in 2014, skipping the 22-nm node. The foundries schedule seems to be planed not to be falling too far behind Intel. IBM is the only major company adopting FDSOI for 28-nm and beyond. IBM was not successful in manufacturing any FDSOI and ETSOI after exit from PDSOI as the gate length shrinks. Now IBM Mendez reveals a bold roadmap that skips all technology nodes such as 28nm and 22nm and offers 14nm FDSOI at the same time as Intelís 14-nm FinFET, and claims the same transistor performance with much lower costs. But the roadmap is unrealizable because of the following reasons:
1) Intel has gained very valuable/critical learning through 22-nm FinFET process development and manufacturing that will help enormously for quick fix of the problems, thus quick transition to 14-nm and beyond. IBM, on other hand, canít get such learning by skipping the 28-nm and 22-nm FDSOI. As a result, IBM will encounter a larger number of unknown process/manufacturing problems at 14-nm FDSOI, thus will take much longer time and spend more
resources to detect and fix the unknown problems.
2) Successful implementation of FinFET or FDSOI will be comparatively easier at 22-nm than 14-nm. Intelís orderly approach to 14-nm FinFET without skipping the nodes will win out eventually.
3) 14-nm FDSOI will require an ultrathin approximately 3.5-nm channel layer to suppress transistor leakage current. IBM has to manufacture such thin layer by itself because Soitec canít deliver it. What Soitec can deliver is the minimum thickness of 12-nm channel layer for the 28nm technology node wafer. How much such a wafer will cost for IBM if it were manufacturable?
In my opinion Mendez roadmap for 14-nm FDSOI will not be achievable in 2014. IBM 14-nm FDSOI will be at least two years behind Intelís 14nm FinFET or more. Skim
10 nm seemed to be the limit a while ago but I believe Intel has a 7 nm and 5 nm nodes on their roadmap. More incredible to me is that some feel that they will be able to extend immersion to sub 10 nm! One is left with the question will EUV ever reach mass production?
"A summary slide from Horacio Mendez, executive director of the SOI Consortium, showed the jump with the comment that 14-nm FDSOI would be offered at the same time as Intel's 14-nm FinFET and would show the same performance characteristics but realizable at much lower cost."
Any $ and cent? I don't think so
Bohr stated that Intel looked at both - SOI and bulk and concluded bulk would have a slight cost advantage.
SOI is somewhat "masking" the issue of fin height variation - at least my understanding.
So if Intel can do it with bulk than they are far ahead - Intel continues to minimize height variation which will continue to be advantage at even smaller geometries
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...