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krisi
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re: London Calling: Could gate-switched FDSOI win?
krisi   12/13/2012 12:43:15 AM
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I am not sure I understand. What Asenov simulate is semiconductor device with a certain gate stack. In the simulator it doesn't matter whether the gate is processed first or last, it is just there. What am I missing here? Kris P.s Disclaimer: I has been a while since I used Pisces, Medici or Silvaco's software, but the basic principle remains the same I think

Tony Lange
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re: London Calling: Could gate-switched FDSOI win?
Tony Lange   12/13/2012 2:34:26 AM
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It is about process: the following explanation is from Professor Asenov's blog: In metal-gate-first the implantation and activation of the self-aligned source and drain result in the polycrystalisation of the metal gate. In the commonly used TiN metal gate the resulting average metal grain size is 5-6nm. It is believed that in the gate-last technology the metal gate, deposited after the implantation activation, will not suffer high temperature treatments and can be kept amorphous, thus eliminating MGG as a source of statistical variability.

krisi
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re: London Calling: Could gate-switched FDSOI win?
krisi   12/13/2012 3:56:15 PM
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thank you Tony...so the difference boils down to whether metal gate is amorphous or polycrystalline, right?...but I thought semiconductors can be amorphous, poly or mono but metals are metals, they can't be polycrystalline etc???

pinhead1
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re: London Calling: Could gate-switched FDSOI win?
pinhead1   12/13/2012 5:44:15 PM
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I think metals generally do have crystalline structure, but the grain size is typically very small. I think that during a high temperature anneal, there could be regrowth that you wouldn't get if you skipped the anneal. However, I'm still not sure I buy the TCAD result. Advanced CMOS uses very short anneals to keep the junction shallow, and it's possible that clever engineering of stress films or dopant in the metal gate or something might impede recrystallization.

Peter Clarke
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re: London Calling: Could gate-switched FDSOI win?
Peter Clarke   12/14/2012 2:26:20 PM
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The issue is the variability of the structures. Professor Asenov has extrapolated from bulk CMOS where it is the case that gate-last provides for less varitability in structures and therefore the ability to run devices over wider voltage ranges. Data is starting to come in from LETI/STMicroelectronics that supports the superioity of gate-first FDSOI over bulk CMOS and Professor Asenov has been able to calibrate his TCAD simulation against some of that data. But his point is that gate-last FDSOI should be even better and represents an opportunity for Samsung or TSMC or indeed any of the few companies that are left in leading-edge semiconductor manufacturing.



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