Sounds like high stakes liar's poker...like when Toshiba gave many papers on trench DRAM for next node at that time, and then stuck to planar and grabbed the market while competitors were attempting trench...one node too soon. (At least that is how I remember it long ago). R/D papers vs real fast ramp manufacturing leads to dangerous guessing. Colonel Boyd's disruptive jet dog fights in Korean war beat back the faster MIG's and saved US pilots and planes, using random "early moves" to tire the enemy, costing them the battles. Strike when the enemy is tired...or broke.
Gate first and gate last drive some very different ground rules. So never underestimate the power of a designer to influence ground rules if he or she is intent on scaling their design from one node to the next rather than redesigning.
Solid State technology just reported that IBM presented a paper on advanced 22nm processing and they are using gate first - I repeat gate first!
I am baffled.
IBM would have to think long and hard before giving up control of wafer manufacturing and seeding it to a foundry like GF. The decision point for them is obviously what happens when 450 mm is required. Do they make that huge investment in another FAB ? Everyone down plays the importance of hardware in their product mix, but a great deal of their profit is generated, by, and around, system Z a unique microprocessor. Do they want to become just another foundry customer and tie their destiny to another company?
I think IBM has a pretty meaningless share of the advanced node foundry business. They do develop and manufacture the technologies, but most of their capacity is for internal consumption. I assumed that this is why he left them out of his list.
I think his list is self serving anyhow. SMIC and UMC are probably both going to play in the advanced node space sooner or later (heck, UMC is probably already there).
“If customers want 10-nm by next year, we’ll be there,” he concluded.
I admit I only glanced at it but this caught my eye - is he serious?
Morris Chang was talking about building a dedicated fab for large customer(s) - to me this approach is closer to the IDM model rather the foundry model.
The real economic challenge the way I see it is tremendous amount of fix cost that require very, very large unit volume ramping up quickly.
ASML made some interesting comments in regards to litho IDM process versus foundry process.
Due to design rules/shrink factor foundries would not be able to use multi patterning @14nm -
they would need EUV and it's doubtful EUV will be production worthy by that time while Intel can fall back on multi patterning
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.