Well, I have to say that this is all jolly exciting. When we first started to hear about things like SoC FPGAs that combined dual ARM Cortex-A9 processors with programmable digital FPGA fabric, I must admit that I did wonder what the design tools would look like. Now I have my answer.
The great thing here is that when the FPGA designers create any hardware accelerator blocks and functions in the FPGA fabric, their register maps are automatically made available to the software developers just the way they are used to.
Also, this combined Altera/ARM environment allows software developers to set breakpoints in their code that will trigger data/signal capture in the FPGA fabric; similarly, th ehardware designers can set up SignalTap virtual logic analyzer triggers in the programmable fabric that will cause breakpoints in the software.
With regard to the ARM debugger -- this is a full-up implementation without any limitations -- except for the fact that it's locked to the Altera FPGA SoC. This type of high-end debugging capability (the ability to look at Linux threads, semaphores, queues, etc) could easily cost up to $5000 or more. so including it with the Altera tools for only $995 is pretty mind-blowing.