My understanding is that 14-nm FDSOI is the new name for what was 20-nm FDSOI.
And that it will be offered in 2014 at approx. the same time as 14-nm FinFETs from Intel, the 14XM process from Globalfoundries and 16-nm FinFET process from TSMC.
1. 14nm SOC is equals "20nm density design rules"
2. 16nm TSMC finFET equals 20nm density design rules"
3. 14nm Global FinFET is equals "20nm density design rules"
4. 10nm TSMC equals 14nm density design rules (S=0.7 scale factor from 20nm).
Business orders are are for 20SOC (planar). No business model to redesign all the functional block IP to finFET or FDSOI at same density.
10nm will be SOI for all process variants HP/LP
Word is Altera told TSMC they see no value in "20 nm FinFET" called "16nm node"
16nm is a Die size increase from 20 nm SOC and no power savings since FDSOI has body bias (key in FPGA) and no Body Bias in FinFETs.
Altera will use TSMC 20nm and look for other options.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.