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song-chou-1
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re: Altera eyes FDSOI process for FPGAs
song-chou-1   12/16/2012 10:36:47 PM
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Mr. Peter, Word is Altera told TSMC they see no value in "20 nm FinFET" called "16nm node" 16nm is a Die size increase from 20 nm SOC and no power savings since FDSOI has body bias (key in FPGA) and no Body Bias in FinFETs. Altera will use TSMC 20nm and look for other options.

song-chou-1
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re: Altera eyes FDSOI process for FPGAs
song-chou-1   12/16/2012 10:40:49 PM
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and 14nm FDSOI is also 20nm? Even me getting confused by the node names

Peter Clarke
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re: Altera eyes FDSOI process for FPGAs
Peter Clarke   12/17/2012 2:09:45 PM
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@Song-chou-1 My understanding is that 14-nm FDSOI is the new name for what was 20-nm FDSOI. And that it will be offered in 2014 at approx. the same time as 14-nm FinFETs from Intel, the 14XM process from Globalfoundries and 16-nm FinFET process from TSMC.

BJ-5
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re: Altera eyes FDSOI process for FPGAs
BJ-5   12/17/2012 1:59:29 PM
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Song Chou, 1. 14nm SOC is equals "20nm density design rules" 2. 16nm TSMC finFET equals 20nm density design rules" 3. 14nm Global FinFET is equals "20nm density design rules" 4. 10nm TSMC equals 14nm density design rules (S=0.7 scale factor from 20nm). Business orders are are for 20SOC (planar). No business model to redesign all the functional block IP to finFET or FDSOI at same density. 10nm will be SOI for all process variants HP/LP



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