Nice work and good analysis. Do you think the bWL architecture can be exended to 2x nm node? I think the cell capacitance is also an issue at 2x nm and higher density requirements may push to look for other memory alternatives beyond 2x node.
Yes bWl can be extended to 2x node by changing layout to 4F2.
There are some processing issues but 4F2 with bWL is possible.
For increasing cell capacitance, apart from looking at new dielectrics, there are some other tricks like using amorphous layers.
The industry is always looking for other memory alternatives and it will come...
It doesn't make sense to call it a 3xnm node when it is in reality a 4xnm DRAM technology. The reduced cell size would not justify this naming convention, since the competitors Samsung and Micron are using 6F2 designs allready.
What about the IP situation, did Hynix buy the the bWL patents out of the Qimonda bankruptcy assets?
Micron & Samsung have been using 6F2 layout since many generations. So layout is not an indication of tech-node.
In the early days for logic devices for defining the tech-node gate length was the main parameter then it became metal-1 pitch and the contacted gate pitch but now the most reliable parameter is the 6T-SRAM cell area.
Cell area will emerge as important criteria for DRAM too.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.