Relative success at the very leading edge of non-volatile memory development challenging Flash,i.e.MRAM, PCM, FeRAM ReRAM, CBRAM CNT-RAM etc. can only really be measured by a league table of design-in wins. In the past claims and counter claims that are for the most part the chatter of promoters selling futures have plagued many NV technology developments. More recently the claim, see
Quote “………Micron will ship tens of millions of units of 1-Gbit PCM in 2012 in 45-nm process in its leading-edge component, which combines a 1-Gbit PCM die with a 512-Mbit SDRAM and provides a LPDDR2 interface………”
A claim that was associated with an actual design win that has needed the near term shipping numbers to be modified down wards when more closely scrutinized by us. It was a claim that perhaps had more to do with enthusiasm than reality.
So please, bring on the design-in wins league table as the way of providing true measure of NV memory potential and success.
The PC is still the center of the universe for most. Phones are much more capable but nobody would even consider buying a PC with the current technical limitations of a phone on storage, bandwidth, and processing power. Not to mention the screen, although the ability to hook up to HD TV's really obviates this limitation.
I have worked on requirements for airborne military computers. Customers do not like using capacitors to maintain CMOS RAM when power is down. But they generally do not have a problem using capacitors to store enough charge to copy volatile memory to NVM when power goes down. In addition, some simple algorithms can be developed that copy those parts of CMOS RAM to NVM that have been updated by do not appear to be changing that much, leaving the task of saving those parts of CMOS that do change frequently only when power goes out.
The main problem with SSDs is wearing them out from the continuous writing to the index tables. The solution is to design a multi-technology SSD; a CMOS RAM based area where the indexes are stored and then the non-volatile memory for the data files themselves.
During a loss of power the SSD will need sufficient capacitive storage to copy the CMOS RAM to some NV memory. When power is restored, the CMOS is reloaded from NV RAM and the disk is ready to operate.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.