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R G.Neale
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re: Top 5 memory trends for 2013
R G.Neale   2/13/2013 12:52:31 AM
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Relative success at the very leading edge of non-volatile memory development challenging Flash,i.e.MRAM, PCM, FeRAM ReRAM, CBRAM CNT-RAM etc. can only really be measured by a league table of design-in wins. In the past claims and counter claims that are for the most part the chatter of promoters selling futures have plagued many NV technology developments. More recently the claim, see http://www.eetimes.com/electronics-news/4401477/Electronica--Micron-memory-to-skip-a-node Quote “………Micron will ship tens of millions of units of 1-Gbit PCM in 2012 in 45-nm process in its leading-edge component, which combines a 1-Gbit PCM die with a 512-Mbit SDRAM and provides a LPDDR2 interface………” A claim that was associated with an actual design win that has needed the near term shipping numbers to be modified down wards when more closely scrutinized by us. It was a claim that perhaps had more to do with enthusiasm than reality. So please, bring on the design-in wins league table as the way of providing true measure of NV memory potential and success.

selinz
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re: Top 5 memory trends for 2013
selinz   2/12/2013 7:06:50 PM
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The PC is still the center of the universe for most. Phones are much more capable but nobody would even consider buying a PC with the current technical limitations of a phone on storage, bandwidth, and processing power. Not to mention the screen, although the ability to hook up to HD TV's really obviates this limitation.

DadOf3TeenieBoppers
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re: Top 5 memory trends for 2013
DadOf3TeenieBoppers   1/14/2013 4:59:53 PM
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I have worked on requirements for airborne military computers. Customers do not like using capacitors to maintain CMOS RAM when power is down. But they generally do not have a problem using capacitors to store enough charge to copy volatile memory to NVM when power goes down. In addition, some simple algorithms can be developed that copy those parts of CMOS RAM to NVM that have been updated by do not appear to be changing that much, leaving the task of saving those parts of CMOS that do change frequently only when power goes out.

DadOf3TeenieBoppers
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re: Top 5 memory trends for 2013
DadOf3TeenieBoppers   1/14/2013 4:55:44 PM
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The main problem with SSDs is wearing them out from the continuous writing to the index tables. The solution is to design a multi-technology SSD; a CMOS RAM based area where the indexes are stored and then the non-volatile memory for the data files themselves. During a loss of power the SSD will need sufficient capacitive storage to copy the CMOS RAM to some NV memory. When power is restored, the CMOS is reloaded from NV RAM and the disk is ready to operate.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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