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krisi
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re: DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
krisi   1/11/2013 5:21:09 PM
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What kind of clock recovery architecture is used at 25 Gb/s?

rick merritt
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re: DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
rick merritt   1/11/2013 5:22:59 PM
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What bugaboos are you wrestling with at 25G?

EDWARDP.SAYRE
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re: DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
EDWARDP.SAYRE   1/11/2013 7:59:45 PM
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NESA has worked on high speed serial problems for a long time (see EE Times, 8/17/1998). Some of the major problems for the IEEE 25/100 Gbps 802.3bj committee are the important design concepts to specify and how they relate to the IEEE 10/40 Gbps 802.3ae technology. From a physical designers point of view, a major problem is where and how to find and accumulate the technical application notes and form a coherent end to end reliable design. Few tools are appropriate for this level of design. A deep appreciation of advanced fundamentals as they relate to PCB materials, microwave and digital interconnect theory and design are required. Consultants such as myself and Scott McMorrow can fill the gap where there isn't a large and experienced SI staff. Sincerely, Ed Sayre, CTO North East Systems Associates, Inc. (NESA)

docdivakar
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re: DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
docdivakar   1/21/2013 6:46:43 PM
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Rick: the solution for handling losses caused by the woven glass PCB's is one part of the solution -I would imagine it ensures a more uniform dielectric field alleviating the need for more expensive dielectrics. The other that is mentioned hits home to me -package is going to be a big issue. In addition to routing challenges for the exploding number of connections, minimizing reflections at the package-to-board interface is indeed a problem at higher signaling rates. MP Divakar

Yang Zhiwei
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re: DesignCon SMEs: Tough Path to 25G+ High-Speed Signals
Yang Zhiwei   1/23/2013 3:53:26 AM
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Anything else to say, expect it!



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