The main reason that the 14nm costs are not significantly higher than the 20nm costs is that the 14nm process is not a linear shrink of the 20nm process. It is essentially a 20nm process with a 14nm FinFET transistor. So all the back end multi-patterning costs are identical to 20nm. You will see the cost curve go back on the projected track at 10nm when triple patterning and SADP start needing to be used.
The NV memory vendors has already embrace monolithic 3D as their path to keep Moore's Law (which is about cost and number of transistors and not about dimension. The logic vendors should adapt the 3D path as in addition to provides a better cost it provides far lower power. On chip interconnect is now domination logic IC power and monolithic 3D is the only practical path to increase complexity without increasing power.
Technology always come with challenges that need to be engineered. And monolithic 3D will introduce its own engineering challenges. As to the heat removal we did present in IEDM 2012 joint paper with Stanford presenting the strategy to overcome the heat removal challenge as been presented in our recent Blog http://www.monolithic3d.com/2/post/2012/12/can-heat-be-removed-from-3d-ic-stacks.html.
The more important aspect is the total power which is becoming the important limiting factor. In that respect monolithic 3D is becoming the best path to overcome this limit as on chip interconnect is now dominating ~80% of the device power as presented in this IEDM
As you pointed out, there is a difference between foundries and Intel perspectives. As I pointed out, but you deleted, the difference is sensitivity to mask cost/product volume. A few more masks may be more tolerable if the volume is higher. But if there are respins of product, certainly mask cost burden is a bigger issue. E-beam maskless was proposed to completely eliminate the sensitivity, but perhaps more efficient multipatterning will arrive sooner.
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