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bgees
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re: DesignCon 2013 keeps the focus on memory
bgees   2/4/2013 5:17:53 PM
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After attending several sessions and seeing the demonstrations in the show floor, I still stand firm with my belief system that: (DDR4 + SoC) = RIP There is no more room for DDR4 into SoC market, it will continue to be standard memory for Server and PCs in multi-drop buses for 2 or 3 chipsets. But the level of expertise require to design, bring up and validate DDR4 memory interface it far more complicated that any SoC interface out there (even harder than 10G-KR). I said this back in 2009 and I continue to stay firm on this matter. There is really no life for DDR4 in SoC other than Hype! This brings us to the key questions, what would all the Next Gen SoC use for external Memory interface? (reply if you think u know the answer!!)



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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