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re: UMC copper process targets power management ICs
docdivakar   2/21/2013 10:55:23 PM
Kris, this is about a decade-old technology developed by TI (was using 15micron Cu back then) and was used in its Swift group of Power Management products. The TPS54672 (with integrated MOSFETs) used a 0.8um BiCMOS process in a TSSOP PowerPAD package and the die used thick Cu in an RDL process which was done typically in a backend fab in those days. I believe the process technology was developed by Unitive with TI's active participation (Unitive has since been a part of Amkor). Since the Swift product days, the backend metallization for thick Cu has further improved. The article doesn't mention about patent claims TI had that prevented a number of other PMIC companies from using this technology. MP Divakar

Clif Tsai
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re: UMC copper process targets power management ICs
Clif Tsai   1/17/2013 8:50:45 PM
Hope the wafer-packaging foundry collaboration will be smart enough to create a robust interconnect system using Cu wire/bump to resolve some of the Cu-based interconnect issues in assembly process and reliability.

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re: UMC copper process targets power management ICs
Kresearch   1/16/2013 8:56:51 PM
It is just a marketing tactic to combine UMC(wafer Foundry) and Chipbond(Bumping house) services. Solution would be like typical RDL process. Anything new? It seems not.

Peter Clarke
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re: UMC copper process targets power management ICs
Peter Clarke   1/16/2013 6:45:18 PM
Well copper is highly contaminating in a fab, so I suspect that UMC/Chipbond are plating copper on to a die as final metal layer step, possibly out of the fab. So then the question is one of desiging PMICs for greater current and thermal performance and which conventional BCD processes you apply the thick-copper plating.

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re: UMC copper process targets power management ICs
krisi   1/16/2013 3:37:54 PM
20% lower resistance doesn't sound like much...I am surprised that would developed a special process option for this...why not use it across the board?


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