Breaking News
Comments
Newest First | Oldest First | Threaded View
docdivakar
User Rank
Manager
re: UMC copper process targets power management ICs
docdivakar   2/21/2013 10:55:23 PM
NO RATINGS
Kris, this is about a decade-old technology developed by TI (was using 15micron Cu back then) and was used in its Swift group of Power Management products. The TPS54672 (with integrated MOSFETs) used a 0.8um BiCMOS process in a TSSOP PowerPAD package and the die used thick Cu in an RDL process which was done typically in a backend fab in those days. I believe the process technology was developed by Unitive with TI's active participation (Unitive has since been a part of Amkor). Since the Swift product days, the backend metallization for thick Cu has further improved. The article doesn't mention about patent claims TI had that prevented a number of other PMIC companies from using this technology. MP Divakar

Clif Tsai
User Rank
Rookie
re: UMC copper process targets power management ICs
Clif Tsai   1/17/2013 8:50:45 PM
NO RATINGS
Hope the wafer-packaging foundry collaboration will be smart enough to create a robust interconnect system using Cu wire/bump to resolve some of the Cu-based interconnect issues in assembly process and reliability.

Kresearch
User Rank
Rookie
re: UMC copper process targets power management ICs
Kresearch   1/16/2013 8:56:51 PM
NO RATINGS
It is just a marketing tactic to combine UMC(wafer Foundry) and Chipbond(Bumping house) services. Solution would be like typical RDL process. Anything new? It seems not.

Peter Clarke
User Rank
Blogger
re: UMC copper process targets power management ICs
Peter Clarke   1/16/2013 6:45:18 PM
NO RATINGS
Well copper is highly contaminating in a fab, so I suspect that UMC/Chipbond are plating copper on to a die as final metal layer step, possibly out of the fab. So then the question is one of desiging PMICs for greater current and thermal performance and which conventional BCD processes you apply the thick-copper plating.

krisi
User Rank
CEO
re: UMC copper process targets power management ICs
krisi   1/16/2013 3:37:54 PM
NO RATINGS
20% lower resistance doesn't sound like much...I am surprised that would developed a special process option for this...why not use it across the board?



EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

10 Top Video Parodies on User Interfaces
Max Maxfield
8 comments
As you may know, the people of Scotland are holding a referendum today to decide whether they wish to remain part of the United Kingdom (UK) or to become fully independent and "go it ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)