I read the Cyclos white paper with great interest. The resonant concept is simple but it may be too simple. The white paper focuses heavily on clock tree power and skew - to be sure these are vitally important aspects of IC design - but so is jitter. In certain applications jitter can be a show-stopper and my engineering sense tells me that a parallel resonant tuned clock tree (being of high impedance) would be very susceptible to jitter generated from crosstalk.
I, on the other hand, enjoy clicking once for each word in the article.
This is especially effective on slower browsers, where the densely-populated and expertly-coded EET web page takes torturous seconds to load and I stop reading the article, but am _sure_ to read the advertisements, v e r y s l o w l y.
Appreciate these techonology development insights. But, . . ., one quarter column worth of reading material in each click? My 1920 x 1080 laptop screen can fit at least six of these slides in a screenful. I understand the need for sponsors and advertisements; but with all the formatted content on this page, inclidng the ad, occupy less than 50% of my screen, with two large white margins left open on either side. For reading convenience, please consider posting at least two of these slides on each page.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.