@supersonic76, I was checking up on this. Indeed, I would think even 32 nm hp is not yet nailed down, given the serious LER (well exceeding 10%). That's why there has even been talk of EUV being used in double patterning context, like complementary lithography proposed by Intel. Of course, consideration of double patterning defeats purpose of considering EUV.
I believe they run test structures.
There is some data that is private and some that is communal.
I suspect some wafers are communal and some private and confidential.
Things like lithography metrics benefit from totalling everybodies' wafers.
For technologies which are equally extremely high risk to all companies (like EUV), it makes sense to have the collaboration model, with actual data and information being shared. For technologies of unequally high risk (like FinFETs) the value may be realized only for some companies, e.g., Qualcomm instead of Intel in the case of FinFETs.
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...