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de_la_rosa
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re: Qualcomm joins IMEC core CMOS R&D program
de_la_rosa   1/30/2013 3:22:56 PM
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Do u mean test structures at 22nm or below? Because this is where i get confused. Has anybody seen decent results from an EUV platform? I saw once a 32nm half pitch pattern about 6 months ago.

Peter Clarke
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re: Qualcomm joins IMEC core CMOS R&D program
Peter Clarke   1/30/2013 6:39:19 PM
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I believe they run test structures. There is some data that is private and some that is communal. I suspect some wafers are communal and some private and confidential. Things like lithography metrics benefit from totalling everybodies' wafers.

de_la_rosa
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re: Qualcomm joins IMEC core CMOS R&D program
de_la_rosa   1/31/2013 12:56:36 PM
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Perhaps true for resist and process R&D. Difficult to see the benefits for chip manufactures though since there is no evidence asml's EUV platform can print below 32nm. Correct me if i am wrong.

de_la_rosa
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re: Qualcomm joins IMEC core CMOS R&D program
de_la_rosa   1/31/2013 4:30:11 PM
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I wish eetimes would report facts rather than buy into the politics

resistion
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re: Qualcomm joins IMEC core CMOS R&D program
resistion   2/2/2013 3:18:59 AM
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@supersonic76, I was checking up on this. Indeed, I would think even 32 nm hp is not yet nailed down, given the serious LER (well exceeding 10%). That's why there has even been talk of EUV being used in double patterning context, like complementary lithography proposed by Intel. Of course, consideration of double patterning defeats purpose of considering EUV. http://www.euvlitho.com/2012/P36.pdf

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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