Breaking News
Comments
resistion
User Rank
CEO
re: Cisco packs silicon photonics on 3-D ICs
resistion   1/29/2013 4:13:20 AM
NO RATINGS
The lasers are still non-Si; they are probably InP or the like at the very least. So it looks like interposers will replace motherboards? That's pretty disruptive. Expect some resistance.

a.sun
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
a.sun   1/29/2013 7:24:35 PM
NO RATINGS
The laser is made of InP by bonding a 2-4" InP wafer onto a 6-8" Si wafer (the size mismatch is an issue!) and thinning down the InP wafer to a few micrometers for later planar processing steps. As far as I know, Intel's solution uses separate CMOS TIA & laser driver chips in addition to a Si photonics chip (including functions of photo detection, modulation and optical routing) in comparison to a more integrated solution from Luxtera.

a.sun
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
a.sun   1/29/2013 7:25:23 PM
NO RATINGS
The laser is made of InP by bonding a 2-4" InP wafer onto a 6-8" Si wafer (the size mismatch is an issue!) and thinning down the InP wafer to a few micrometers for later planar processing steps. As far as I know, Intel's solution uses separate CMOS TIA & laser driver chips in addition to a Si photonics chip (including functions of photo detection, modulation and optical routing) in comparison to a more integrated solution from Luxtera.

resistion
User Rank
CEO
re: Cisco packs silicon photonics on 3-D ICs
resistion   1/31/2013 7:57:51 AM
NO RATINGS
Thanks for the information. Is this available somewhere? Thanks again.

a.sun
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
a.sun   2/2/2013 4:40:05 PM
NO RATINGS
First reported bonded laser on SOI was a joint project that Intel and UCSB worked on a couple of years ago. Some collaborating European groups independently developed the same thing but with a different III-V active material nearly the same time. I remember Intel&UCSB published their results in a fast review cycle journal to beat their opponents. Bonded lasers in principal suffer from lower performance by using SOI waveguide as external lasing resonator, let alone the complexity in processing (but which can be conquered) and size mismatch between InP wafers and Si wafers. But I heard some improvement recently. Intel didn't push very hard in fully monolithic integration of photonic components and CMOS circuits for TIA and laser driver. Luxtera spent a ton of money and nearly a decade on incorporating photonic components in a legacy 130nm line of Freescale which is only good for upto 10G. 25G TIA&driver needs at least 65nm which need too much design rule and library changes to have photonics in. This is much harder than mixing digital and analog circuits which still meets troubles from time to time. It may worth doing, but you definitely need someone with deep pocket.

rick merritt
User Rank
Author
re: Cisco packs silicon photonics on 3-D ICs
rick merritt   1/29/2013 6:07:37 AM
NO RATINGS
But not as much resistance as an off-chip design ;-)

Turkman
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
Turkman   1/30/2013 3:53:21 PM
NO RATINGS
I knew that comment would induce someone to make a joke.

resistion
User Rank
CEO
re: Cisco packs silicon photonics on 3-D ICs
resistion   1/31/2013 7:58:37 AM
NO RATINGS
It's a good one ;)

HS_SemiPro
User Rank
CEO
re: Cisco packs silicon photonics on 3-D ICs
HS_SemiPro   1/29/2013 6:37:11 AM
NO RATINGS
That's the beauty of 2.5D and full 3D designs, greatly reduce system cost improve signal latency

a.sun
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
a.sun   1/29/2013 7:29:40 PM
NO RATINGS
Unfortunately, the integration of these different optical components like lens and laser can be done in a identical thus cost effective way like 2.5D electronics. Different bonding/soldering techniques and tolerances exist for different components, i.e. laser requires sub-micro placement accuracy. So up to now, it's merely a reduced scale of optical packaging on Si instead of on submount.

a.sun
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
a.sun   1/29/2013 7:34:40 PM
NO RATINGS
I meant "can't be done in ...". btw, is there a way to edit one's own posts? It's not uncommon to make typos from time to time. It should be a basic function.

docdivakar
User Rank
Manager
re: Cisco packs silicon photonics on 3-D ICs
docdivakar   1/29/2013 7:27:17 PM
NO RATINGS
Rick, the title is somewhat misleading... I think Mr. Swift was referring to planar Si optical waveguides. Using these in 3D optical interconnect, from today's on-chip optical interconnect technology, is still far away from fruition from a practical view point. Last year's DesignCon I think there was a talk by HP Lab's chief about this but it has remained largely as a research project. There is no doubt that this is the next growth area for transistors. Underwhelming SDN/OpenFlow by Cisco is not surprising because it is a disruptor to their legacy products! For those interested, here is the link to presentations from Silicon Valley Comsoc on SDN's by Guru Parulkar & Dan Pitt of Open Networking Research Center: http://ewh.ieee.org/r6/scv/comsoc/ComSoc_2012_Presentations.php MP Divakar

rick merritt
User Rank
Author
re: Cisco packs silicon photonics on 3-D ICs
rick merritt   1/29/2013 9:01:04 PM
NO RATINGS
@Divakar: Thanks for the SDN link. Yes, a potentially huge disruption for Cisco! Swift was so vague it's hard to tell exactly what Cisco is planning with 2.5-D and optics but your guess is more technically informed than mine!

krisi
User Rank
CEO
re: Cisco packs silicon photonics on 3-D ICs
krisi   1/29/2013 10:04:42 PM
NO RATINGS
Sounds like pretty disruptive technology if they can pull it off in mass production...would anyone be interested in discussing it at Grenoble emerging technologies symposium, details at www.cmosetr.com? planning a panel discussion on this topic, kris.iniewski@gmail.com

rick merritt
User Rank
Author
re: Cisco packs silicon photonics on 3-D ICs
rick merritt   1/29/2013 10:40:35 PM
NO RATINGS
@Kris: I sent an email to Luxtera, Kotura, Intel, Cisco contacts on this

athose
User Rank
Rookie
re: Cisco packs silicon photonics on 3-D ICs
athose   3/20/2013 4:14:52 AM
NO RATINGS
here is some thing that may interest people as possibly some thing that may be ahead of this. Opel Laser Uses POET Optoelectronic Platform The III-V gallium arsenide (GaAs) based monolithic platform could change the roadmap for smartphones, tablet and wearable computers Opel's U.S. affiliate, Odis Inc. has produced an integrated laser device in its Planar Optoelectronic Technology (POET) process. The laser enables high-performance devices fusing optical and electronic devices together on a single chip. After years of development, the fabrication of the first Vertical Cavity Laser, (VCL) utilising Odis'patented POET GaAs III-V technology is a significant success. Incremental progress over the years has led to what many consider to be the next phase of semiconductor development which is to surpass the capabilities of complementary metal oxide semiconductor (CMOS) technology for the next generation of high speed low power applications. The POET advantage is the merging of optical devices into the growth and fabrication that supports complementary HFET analogue and digital functions. The intimate connections between diverse device types enables novel gate designs which dramatically reduce the power consumed in the opto-electronic (OE) and electro-optic conversions. The VCL has the small footprint required for dense circuit layout and enables vertical connections from anywhere in the circuit plane to fibre or to other stacked chips. Moving forward, development will lower the threshold current, increase the output power and optimise the in-plane version of the VCL. Also, the complementary transistor circuit capability will be enhanced by reducing the feature size to the 100 nm scale incorporating Odis' new self-aligned contact technology. With transistor cutoff frequencies around 38 GHz for a 0.7µm gate, the scaling is expected to produce 260 GHz transistors with big improvements in circuit speed.



EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

How to Fly Without Catching the Dreaded Lurgy?
Max Maxfield
19 comments
I am currently not wearing my happy face. In fact, I am a "poorly soldier," as my mother would say when I was a little lad.

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
19 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)