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chipmonk0
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re: UMC, Stats ChipPac team for 3-D IC demo
chipmonk0   1/30/2013 9:24:58 PM
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In order to gain credibilty this group would have to publish technical details - the sooner the better. What were the bandwidth and power needed to transfer data ? Include construction details and all electrical / functional tests carried out.

docdivakar
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re: UMC, Stats ChipPac team for 3-D IC demo
docdivakar   1/30/2013 5:00:06 PM
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Nice move, the open ecosystem part is appealing; how ever, is there a clearly defined EDA flow or is it going to be a hodgepodge of piecing together a disparate set of tools? MP Divakar

Kresearch
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re: UMC, Stats ChipPac team for 3-D IC demo
Kresearch   1/30/2013 1:31:40 PM
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I remembered UMC teamed with PowerTech and Elpida in 3DIC ~2 years ago. Now team with Stats ChipPac. This implied something. @Peter could we get more insight?

pica0
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re: UMC, Stats ChipPac team for 3-D IC demo
pica0   1/30/2013 1:11:40 PM
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But independent of the thermal resistance of the interposer the heat surface ratio get worse. One idea to deal with that problem to significally frequncies and over-compensate this with massiv paralellism. As a simple example instead of transmitting 256bit@2GHz, transmit 4Kbit@0.5GHz. Heat dissipation should almost be the same, but the throughtput increased 4x. I know also latency increases 4x.

resistion
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CEO
re: UMC, Stats ChipPac team for 3-D IC demo
resistion   1/30/2013 11:29:43 AM
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Depends on thermal resistance of the interposer.

pica0
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re: UMC, Stats ChipPac team for 3-D IC demo
pica0   1/30/2013 9:30:24 AM
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Heat is even a problem in 2D designs. How do 2.5D or 3D designs deal with heat?

resistion
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CEO
re: UMC, Stats ChipPac team for 3-D IC demo
resistion   1/30/2013 1:13:35 AM
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I worry that the TSV trend will favor the more (only?) vertically integrated electronics company, i.e., Samsung, since there is no standards barrier for them.

chipmonk0
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Manager
re: UMC, Stats ChipPac team for 3-D IC demo
chipmonk0   1/29/2013 4:41:17 PM
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Since TSMC rather aggressively staked out their claim to the whole process flow for TSV based 3-D stacking, the liliputs have been forming consortia. More power to them. But 3D is not yet a mature technology ( immature process steps e,g. high aspect ratio fille TSVs, bond / debond, OR unresolved performance issues: stress and heat related effects on devices in the inner layers ). Its implementation into products, like any new technology will start at the high end ( military, medical implants ),not with Smart Phones, perhaps not even Servers as some Boosters have been promising for a few years. At present much of the hot air is coming from Govt. funded European Research Labs. They do not have an enviable record in Microelectronics.



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