Since TSMC rather aggressively staked out their claim to the whole process flow for TSV based 3-D stacking, the liliputs have been forming consortia.
More power to them.
But 3D is not yet a mature technology ( immature process steps e,g. high aspect ratio fille TSVs, bond / debond, OR unresolved performance issues: stress and heat related effects on devices in the inner layers ).
Its implementation into products, like any new technology will start at the high end ( military, medical implants ),not with Smart Phones, perhaps not even Servers as some Boosters have been promising for a few years.
At present much of the hot air is coming from Govt. funded European Research Labs. They do not have an enviable record in Microelectronics.
But independent of the thermal resistance of the interposer the heat surface ratio get worse.
One idea to deal with that problem to significally frequncies and over-compensate this with massiv paralellism. As a simple example instead of transmitting 256bit@2GHz, transmit 4Kbit@0.5GHz. Heat dissipation should almost be the same, but the throughtput increased 4x. I know also latency increases 4x.
In order to gain credibilty this group would have to publish technical details - the sooner the better. What were the bandwidth and power needed to transfer data ? Include construction details and all electrical / functional tests carried out.
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