Breaking News
Comments
Newest First | Oldest First | Threaded View
resistion
User Rank
Manager
re: Xilinx preps 20-nm IC tape-out
resistion   2/1/2013 5:19:38 PM
NO RATINGS
Intel started double patterning a lot earlier. Due to pitch too small, their 45 nm diffusion and gate contacts had to be separately done with dry 193 nm, for example. This had to continue at 32 nm with immersion of course.

de_la_rosa
User Rank
Rookie
re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/31/2013 8:52:05 PM
NO RATINGS
Well I actually wasn't aware NAND flash was already produced at 20nm. Amazing how far they pushed DUV immersion! Can EUV ever catch up???? EUV sounds DOA. Xilinx can't use double patterning for their designs. So they are surely stuck at the 32nm node for ever.

EUV Guy
User Rank
Rookie
re: Xilinx preps 20-nm IC tape-out
EUV Guy   1/31/2013 6:34:01 PM
NO RATINGS
Memory companies are doing volume manufacturing at 20nm. NAND flash from all major vendors is available at or near 20nm half pitch, achieved with now standard double patterning techniques. Are you referring to Logic ICs exclusively?

de_la_rosa
User Rank
Rookie
re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/31/2013 4:33:22 PM
NO RATINGS
Its simply not true. For very basic structures (lines and spaces) they may achieve 28 nm with double patterning. Nobody is close to 20nm.

resistion
User Rank
Manager
re: Xilinx preps 20-nm IC tape-out
resistion   1/31/2013 4:58:51 AM
NO RATINGS
But how long can a company continue to publicly stay at 28 nm?

Kresearch
User Rank
Rookie
re: Xilinx preps 20-nm IC tape-out
Kresearch   1/31/2013 3:45:23 AM
NO RATINGS
@supersonic76, there are more double patterning layers in 20nm Lithography but no triple in foundry sides.

de_la_rosa
User Rank
Rookie
re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/30/2013 6:35:22 PM
NO RATINGS
I'm really curious how they plan 20nm with DUV Immersion Lithography. Double patterning can provided limited patterns at the 28nm HP. Are they implying plans for triple patterning?? My suspicion is that there is a lot of bluffing going on at the moment.



Most Recent Comments
HitheshM500
 
NIRANKUSH456
 
NIRANKUSH456
 
David Ashton
 
Rich Krajewski
 
sranje
 
MeasurementBlues
 
MeasurementBlues
 
Sanjib.A
Flash Poll
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Don’t 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
3 comments
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
7 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
37 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
140 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)