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resistion
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re: Xilinx preps 20-nm IC tape-out
resistion   2/1/2013 5:19:38 PM
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Intel started double patterning a lot earlier. Due to pitch too small, their 45 nm diffusion and gate contacts had to be separately done with dry 193 nm, for example. This had to continue at 32 nm with immersion of course.

de_la_rosa
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re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/31/2013 8:52:05 PM
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Well I actually wasn't aware NAND flash was already produced at 20nm. Amazing how far they pushed DUV immersion! Can EUV ever catch up???? EUV sounds DOA. Xilinx can't use double patterning for their designs. So they are surely stuck at the 32nm node for ever.

EUV Guy
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re: Xilinx preps 20-nm IC tape-out
EUV Guy   1/31/2013 6:34:01 PM
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Memory companies are doing volume manufacturing at 20nm. NAND flash from all major vendors is available at or near 20nm half pitch, achieved with now standard double patterning techniques. Are you referring to Logic ICs exclusively?

de_la_rosa
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re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/31/2013 4:33:22 PM
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Its simply not true. For very basic structures (lines and spaces) they may achieve 28 nm with double patterning. Nobody is close to 20nm.

resistion
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CEO
re: Xilinx preps 20-nm IC tape-out
resistion   1/31/2013 4:58:51 AM
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But how long can a company continue to publicly stay at 28 nm?

Kresearch
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re: Xilinx preps 20-nm IC tape-out
Kresearch   1/31/2013 3:45:23 AM
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@supersonic76, there are more double patterning layers in 20nm Lithography but no triple in foundry sides.

de_la_rosa
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re: Xilinx preps 20-nm IC tape-out
de_la_rosa   1/30/2013 6:35:22 PM
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I'm really curious how they plan 20nm with DUV Immersion Lithography. Double patterning can provided limited patterns at the 28nm HP. Are they implying plans for triple patterning?? My suspicion is that there is a lot of bluffing going on at the moment.



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