Intel started double patterning a lot earlier. Due to pitch too small, their 45 nm diffusion and gate contacts had to be separately done with dry 193 nm, for example. This had to continue at 32 nm with immersion of course.
Well I actually wasn't aware NAND flash was already produced at 20nm. Amazing how far they pushed DUV immersion! Can EUV ever catch up???? EUV sounds DOA.
Xilinx can't use double patterning for their designs. So they are surely stuck at the 32nm node for ever.
Memory companies are doing volume manufacturing at 20nm. NAND flash from all major vendors is available at or near 20nm half pitch, achieved with now standard double patterning techniques. Are you referring to Logic ICs exclusively?
I'm really curious how they plan 20nm with DUV Immersion Lithography. Double patterning can provided limited patterns at the 28nm HP. Are they implying plans for triple patterning??
My suspicion is that there is a lot of bluffing going on at the moment.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.