I'm really curious how they plan 20nm with DUV Immersion Lithography. Double patterning can provided limited patterns at the 28nm HP. Are they implying plans for triple patterning??
My suspicion is that there is a lot of bluffing going on at the moment.
Memory companies are doing volume manufacturing at 20nm. NAND flash from all major vendors is available at or near 20nm half pitch, achieved with now standard double patterning techniques. Are you referring to Logic ICs exclusively?
Well I actually wasn't aware NAND flash was already produced at 20nm. Amazing how far they pushed DUV immersion! Can EUV ever catch up???? EUV sounds DOA.
Xilinx can't use double patterning for their designs. So they are surely stuck at the 32nm node for ever.
Intel started double patterning a lot earlier. Due to pitch too small, their 45 nm diffusion and gate contacts had to be separately done with dry 193 nm, for example. This had to continue at 32 nm with immersion of course.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.