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yjchen
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re: Reducing power in AMD processor core with RTL clock gating analysis
yjchen   2/8/2013 7:21:26 AM
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Hi Steve, As you mentioned, the correlation between silicon and PTPX are about +/-10%. From your experience, what's the correlation between PowerPro and PTPX? And Powerpro between silicon? Besides, in your flow, the input of Powerpro is saif. Why don't you use real waveform, like vcd or fsdb? Thanks. yjchen

daleste
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re: Reducing power in AMD processor core with RTL clock gating analysis
daleste   2/12/2013 3:29:59 AM
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Good work to improve the efficiency of the design. What ever happened to the clock-less logic that was supposed to make all of this not needed?

old account Frank Eory
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re: Reducing power in AMD processor core with RTL clock gating analysis
old account Frank Eory   2/13/2013 2:18:03 PM
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I find it amazing that after all these years of using clock gating to reduce power, the tools & methodologies continue to improve to such a degree that these types of large power reductions are still possible.

GMN
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re: Reducing power in AMD processor core with RTL clock gating analysis
GMN   2/22/2013 8:54:08 PM
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PowerPro does use VCD and FSDB for more accurate analysis. However, if you are primarily concerned about clock gating efficiency, and not looking for peak power analysis, then SAIF is faster and more efficient

SteveKo
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re: Reducing power in AMD processor core with RTL clock gating analysis
SteveKo   3/1/2013 5:38:54 PM
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GMN had a good reply for SAIF usage, we used the Calypto recommended flow for that technical decision. For PowerPro to PTPX, we were not using their newer version which estimates actual power, we were looking and clock gating efficiency. However, there was useful correlation there. As per table 2, we achieved about a 25% reduction in flop activity rate from one design to the next, and that correlated with about 25% lower dynamic power for typical applications. (As a short point of interest, we did check how much power tended to be used per active flop on one of our early runs. But block-to-block varied a fair bit. As one would expect, blocks with lots of combination logic like floating point had more gate fanout capacitance per flop than other blocks).

SteveKo
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re: Reducing power in AMD processor core with RTL clock gating analysis
SteveKo   3/1/2013 5:42:03 PM
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:-) About 10 years ago we did some serious looking into a clockless X86 design for deep low power, but the toolsets for efficient timing closure weren't there. And providing sufficiently robust async timing for state machines eats into perceived benefits. I think clock trees and meshes with optimized gating strategies will be with us for a while.

SteveKo
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re: Reducing power in AMD processor core with RTL clock gating analysis
SteveKo   3/1/2013 5:46:47 PM
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Indeed, it's interesting that even our max power virus pattern only needs 15% of the flops clocked. There was a lot of designer work optimizing clock gating, but Calypto's SLEC methodology helped show what could be done too. Tools evolve and designers gain experience, leading to ever lower active flop counts.



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