If the FETs are depletion mode devices (most JFETs are, some DMOS are) then think of the circuit as a complementary source follower, with slightly less than unity voltage gain for mid-rail signals. Such circuits are not that unusual as analog domain buffers.
But as I stated above, for logic we have a problem even with such devices, as the voltage gain is always less than unity. Inverters have voltage gain. Non-inverters do not unless they have embedded within them inverters :)
there is a typo in your artikle just above the NOT gate truth table where it says:
"PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VSS (logic 1) via Tr1."
Tr1 of course connects the output to VDD not VSS.
I agree -- what we need now is someone with the required FETs and a test bench -- if all else fails I'll pick some up from Mack Electronics when i visit them on Monday as I just mentioned in the following blog eetimes.com/electronics-blogs/other/4406626/What-light-through-yonder-window-breaks-?Ecosystem=programmable-logic
Yes -- this is a problem whenever the input is switching from 0 to 1 or vice versa, because there is a time in the middle of the switch when both transistors are at least partially active providing a short from Vdd to Vss -- fortunately this occurs for a very short time indeed
the problem lies here in the design itself as ....
when considering the n-mos .... when 'a' terminal is logic 'high' ie equal to 1 then the n-mos transistor is in cutoff mode since the Vgs here would be 1-1=0 thus would be less than Vth ie threshold and thus would not conduct hence the above design is faulty....
Disproving such a proposal is best accomplished by trying it out. Sometimes the results are unexpected and you may learn something. What actually happens when the proposed circuit is constructed? Do the behavior and behavior match the predictions above? With observations in hand, will some adjustments make a difference? [Unfortunately, I don't have the resources to try it out myself.)
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