Breaking News
Comments
Newest First | Oldest First | Threaded View
Page 1 / 2   >   >>
bcarso
User Rank
Rookie
re: My brain hurts!
bcarso   2/13/2013 8:27:11 PM
NO RATINGS
If the FETs are depletion mode devices (most JFETs are, some DMOS are) then think of the circuit as a complementary source follower, with slightly less than unity voltage gain for mid-rail signals. Such circuits are not that unusual as analog domain buffers. But as I stated above, for logic we have a problem even with such devices, as the voltage gain is always less than unity. Inverters have voltage gain. Non-inverters do not unless they have embedded within them inverters :)

Max The Magnificent
User Rank
Blogger
re: My brain hurts!
Max The Magnificent   2/11/2013 11:14:35 PM
NO RATINGS
Arrgghhh!!! Good catch -- I just went back and fixed it -- thanks for the "heads up" -- Max

eugen.saffert
User Rank
Rookie
re: My brain hurts!
eugen.saffert   2/11/2013 9:27:26 AM
NO RATINGS
Hi Max, there is a typo in your artikle just above the NOT gate truth table where it says: "PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VSS (logic 1) via Tr1." Tr1 of course connects the output to VDD not VSS.

Max The Magnificent
User Rank
Blogger
re: My brain hurts!
Max The Magnificent   2/8/2013 6:47:23 PM
NO RATINGS
I agree -- what we need now is someone with the required FETs and a test bench -- if all else fails I'll pick some up from Mack Electronics when i visit them on Monday as I just mentioned in the following blog eetimes.com/electronics-blogs/other/4406626/What-light-through-yonder-window-breaks-?Ecosystem=programmable-logic

Max The Magnificent
User Rank
Blogger
re: My brain hurts!
Max The Magnificent   2/8/2013 6:44:36 PM
NO RATINGS
Yes -- this is a problem whenever the input is switching from 0 to 1 or vice versa, because there is a time in the middle of the switch when both transistors are at least partially active providing a short from Vdd to Vss -- fortunately this occurs for a very short time indeed

Max The Magnificent
User Rank
Blogger
re: My brain hurts!
Max The Magnificent   2/8/2013 6:42:45 PM
NO RATINGS
This is a great answer -- thanks for sharing

ecrahuljain
User Rank
Rookie
re: My brain hurts!
ecrahuljain   2/8/2013 7:06:49 AM
NO RATINGS
the problem lies here in the design itself as .... when considering the n-mos .... when 'a' terminal is logic 'high' ie equal to 1 then the n-mos transistor is in cutoff mode since the Vgs here would be 1-1=0 thus would be less than Vth ie threshold and thus would not conduct hence the above design is faulty....

seaEE
User Rank
CEO
re: My brain hurts!
seaEE   2/8/2013 4:20:56 AM
NO RATINGS
I agree with DrQuine, try it out. Next week we can see if the column is titled Max's Hot FETs.

DrQuine
User Rank
CEO
re: My brain hurts!
DrQuine   2/8/2013 3:31:15 AM
NO RATINGS
Disproving such a proposal is best accomplished by trying it out. Sometimes the results are unexpected and you may learn something. What actually happens when the proposed circuit is constructed? Do the behavior and behavior match the predictions above? With observations in hand, will some adjustments make a difference? [Unfortunately, I don't have the resources to try it out myself.)

David Ashton
User Rank
Blogger
re: My brain hurts!
David Ashton   2/8/2013 12:40:27 AM
NO RATINGS
Fairchild actually put out an app note for using CMOS like this: http://www.fairchildsemi.com/an/AN/AN-88.pdf

Page 1 / 2   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Innovative Technique for Depicting PCBs Using Tiny Figurines
Max Maxfield
12 comments
Following my earlier column on Enhancing Electronic Enterprises With Edison Emanations, I discovered that my chum Alan Winstanley in the UK has a hidden side to him.

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)