The problem with the circuit that he proposed is that the PMOS FET requires a negative voltage on the gate with respect to the source and drain in order to turn on. So in the proposed configuration the voltage at point a would have to be below Vss to turn the PMOS FET on. Similarly, the NMOS FET requires a positive voltage to turn on which would be higher than Vdd.
I would expect it to kind of work, but it should act more like a "des-amplifier". As I see it, when A is high the upper NMOS will look like a diode connected MOS, thus the output voltage Y will never be able to reach Vdd. The same for the lower PMOS device, when A is low, it is connected like a diode and Y will never reach VSS...
Assuming that input "a" can go as high as Vdd, the upper NFET can only pull the output as high as Vdd-Vth, where Vth is the threshold voltage of the NFET. The NFET is in saturation mode (see http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation). Similarly, if "a" can only go as low as Vss the PFET can only pull the output down to Vss+Vth. dneves' description of it as a "des-amplifier" is a good way to put it.
High-side NFETs are often used in power electronics since NFETs are so much more efficient than PFETs, but they have boost circuits to drive the NFET's gate many volts higher than its drain and source.
Proposed circuit seems to be electrical correct, but real integrated circuts are manufactured on "typical" silicon substrate where doped areas has parralel stripes and always NMOS transistor is "higher" and PMOS transistor is "lower" on the picture. Also power lines are distributed to make short connections between Vcc to PMOS and GND to NMOS. Any odds to this rules will make integrated circuit bigger and more expensive.
Layout of not-gate, looks like http://www-scf.usc.edu/~ee577/graphics/magic_tut/magic29.jpg
To put it in simpler terms for those (like myself) that are not analog experts. If one assumes a MOS to behave like an ideal switch all the times, the unconventional buffer design should have worked. The problem resides that one can only approximate the MOS transistors as ideal switches under certain (very strict) conditions. By swapping around the transistors on a standard inverter, the conditions that lead to the MOS behaving like a switch (i.e. in the triode region) are no longer met for both transistors, and those devices will acquire a more complex behavior instead (i.e. saturation region instead). That is why the circuit ends up not working as expected...
Yes -- this is a problem whenever the input is switching from 0 to 1 or vice versa, because there is a time in the middle of the switch when both transistors are at least partially active providing a short from Vdd to Vss -- fortunately this occurs for a very short time indeed
The principal problem is that each part becomes a source follower, which has less than unity gain. Even if the threshold voltages are adjusted in the process to allow for significant output voltage swings, there will always be input to output voltage swing lost. So use with other gates will always be severely constrained.
Basic misunderstanding is that FETs are polarity dependent devices. An N channel FET requires the drain to be more positive than the source, and a P channel requires the opposite. Reversing them, as suggested, reverses the polarities on the FETs and will not work.
Most of the comments above are correct. We also need to remember that the FET source/drain terminals are electrically defined. They can change position with bias and routinely do in techniques such as pass transistor circuits, transmission gates and the like.
In this circuit, just looking at the PMOS, the drain is defined as the top terminal (as long as the output is "high"). Thus, as already pointed out, it is impossible to achieve a -Vgs as required by the PMOS unless Vg is taken to a negative voltage. Ergo, it will not work as you can never get the PMOS "on". The argument for the NMOS is a little different. It can be switched "on" but when the output reaches Vdd-Vth, it turns "off" again.
I suggest that you advise him/her to try it using PSpice or equivalent. It would take 10 minutes or so for it to become completely clear.
In reply to Ed Baker, that indeed happens during switching, and is the source of the so-called "dynamic power" (aFCV^2) that is causing so much trouble at the moment. No smoke, but potential fire as switching power densities get ridiculous :-)
As I recall FETS act not so much as switches but as constant current sources? So if both are on with A at Vdd/2 you'll get a defined current flow through both of them, not a huge (ie smoke-liberating) current. This is used in some applications that use CMOS as linear amps, they're not great but they work.
Disproving such a proposal is best accomplished by trying it out. Sometimes the results are unexpected and you may learn something. What actually happens when the proposed circuit is constructed? Do the behavior and behavior match the predictions above? With observations in hand, will some adjustments make a difference? [Unfortunately, I don't have the resources to try it out myself.)
I agree -- what we need now is someone with the required FETs and a test bench -- if all else fails I'll pick some up from Mack Electronics when i visit them on Monday as I just mentioned in the following blog eetimes.com/electronics-blogs/other/4406626/What-light-through-yonder-window-breaks-?Ecosystem=programmable-logic
the problem lies here in the design itself as ....
when considering the n-mos .... when 'a' terminal is logic 'high' ie equal to 1 then the n-mos transistor is in cutoff mode since the Vgs here would be 1-1=0 thus would be less than Vth ie threshold and thus would not conduct hence the above design is faulty....
there is a typo in your artikle just above the NOT gate truth table where it says:
"PMOS transistor Tr1 will be turned On, and output 'y' will be connected to VSS (logic 1) via Tr1."
Tr1 of course connects the output to VDD not VSS.
If the FETs are depletion mode devices (most JFETs are, some DMOS are) then think of the circuit as a complementary source follower, with slightly less than unity voltage gain for mid-rail signals. Such circuits are not that unusual as analog domain buffers.
But as I stated above, for logic we have a problem even with such devices, as the voltage gain is always less than unity. Inverters have voltage gain. Non-inverters do not unless they have embedded within them inverters :)
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