I first saw ST present on fully-depleted planar SOI technology over 10 years ago -- it's been a long, meticulous journey to reach this point, with a steady stream of papers at the major conferences. The folks at Leti, as well as IBM, ARM, GF, Hitachi, UCBerkeley, Soitec, UCL, Cadence and more have been a major part of this effort, too. This is not a rabbit they've pulled out of a hat. They're getting awesome, silicon-proven results -- especially in terms of cost & power. It looks to me like they've got the right technology at the right time...and now time will tell if they are right.
Yes, from design side would want to reduce well area and switch small area wells.
That would still leave parasitic C under drain junction (for thin BOX) and that would need to be improved from process side (perhaps make box thinner under drain).
To be clear I do think all this is fundamentally solvable.... I just point this out since I think all these type of work needs to be done if FDSOI ever goes mainstream and FDSOI shows its full potential (low variation and low power). FDSOI is a solid concept (perhaps better than bulk 20SOC or bulk FinFET) but it will take an open debate and a few fixes to move concept forward vs. today.
thanks for the discussion
I can confirm your point is correct and identified by TSMC 5 years ago as a flaw in FDSOI. STI trench is needed (cost) and wafer non-planarity would make "hybridization" 0 yield.
See slide 15 for both points
Lastly, the other major issue is strain for high mobility is ineffective in FDSOI.
This limits FDSOI to low performance.
Also has implications on physical IP porting. N/P ratio goes from ~1.3 at 28nm back to ~2. Makes all my physical digital and analog IP non usable without major redesign.
see slide 12 on strain in FDSOI
Adele does not seem to admit problem thin box approach.
can you comment on parasitic capacitance from 3V on UTBB (Asele's recommended 25nm thin buried oxide).
It adds too much extra C and wasted power to be viable.
I would like to thank Mr. Cesana for pointing out: 6nm is 60A, not 0.6A. Since MR. Cesana’s comments are mostly on UTBB, I will respond to FDUTBB. Remember FD UTBB and FDSOI are not the same.
ST video claims that its UTBB behaves like a vertical double gate. It doesn’t. The double gate is an ideal transistor structure having common gates and common source /drain, thus good control of electrostatics and doubling the transistor on-current, Ion. ST’s UTBB has common source and drain, but has two independent gates consisting of two transistors, the top transistor having the proven HK metal gate very reliable used today in semiconductor industry but the bottom transistor having the Si substrate for a gate and the 25-nm thick buried oxide for gate oxide, sharing 7nm channel is totally new and unproven in reliability, performance, and not adopted by semiconductor industry. During UTBB operation a positive 3V is applied to the bottom gate to control Vt of the top gate. How much the transistor I-on is improved by the positive 3V applied to the bottom gate is not shown. Furthermore, some of channel electrons could drift toward the buried oxide and become trapped inside under the 3V positive bias field during UTBB operation, especially near the source region where electron velocity is very slow. Also, a number of interface states could be generated at the thin Si channel-the buried oxide interfaces, and the channel electron mobility could be degraded due to enhanced scattering at the channel-buried oxide interface, resulting in reduced I-on. These could adversely impact UTBB reliability and performance. These phenomena are unique to FD-UTBB because planer bulk, FinlFET, and FDSOI are not substrate biased or grounded during device operation.
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