Here is calculation of very large extra capacitance with your recommended "thin 25nm box" to solve self heating.
Updating what we did 5 years ago and using your thin 25nm BOX recommendation.
Mean n or p-well area size is 100um^2 for a 9 track library at 28nm design (typical for low power design)
For 28nm mean transistor gate oxide is 1.9nm, gate length = 30nm and transistor Width =100nm
Result is (for 25nm BOX) back gate parasitic C is about 2500 times larger than intrinsic gate capacitance for the thin box you recommend
check the math
(100 *1.9)/ (.03*.1 *25.0) = 2533
that is a very very larger extra C to switch (often switched at very large back gate of 1 to 2V ) so that adds a lot of extra power draw.
Pure waist of power without doing useful work and we found block with low activity had higher power in FDSOI with thin box due to this large parasitic C.
So I agree thin box of 25nm helps thermal resistance but that adds too much extra C and removes FDSOI power advantage due to wasted power charging/discharging back gate.
Parasitic C also is on each drain node with this thin of a box as well.
...time to move on from SOI work
thin box 25nm add very very very very very large extra bottom capacitance to each circuit block. Very very very large back gate area. When we switched that at 1 to 2V with any activity factor, power increased for FDSOI with thin box.
I used to work on this and even I have moved on.
TSMC had a major program on PDSOI/FDSOI and partnered with freescale during the past decade.
All that work stopped many years ago due to the issues raised.
SOI self heating is perhaps well understood by some but not understood by foundry customers.
Plus even if I accept its well understood (and its not) none of the ~$20B worth of physical IP qualified by the end of 2013 on 28nm took self heating into account so all that would need to be re-designed and re-qualified: correct?
please tell me where I am in error
....Many blocks have high activity factors: correct?
....and after switching....these blocks slow down on FDSOI: correct?
...,.my IP block needs to be redesigned and requalified? correct?
Also, specifically to ST's flavor of ultra-thin body & box (UTBB) FD-SOI, Giorgio Cesana recently wrote: "- The Buried Oxide (BOX) is extremely thin (only 25nm thick in 28nm technology), offering significantly less thermal resistance;
- The big diodes, the drift MOS, the vertical bipolar, some resistors… are all implemented on the “hybrid” bulk part, eliminating even the thin BOX below them." http://www.advancedsubstratenews.com/2013/02/sts-cesana-further-explains-fd-soi-biasing-more-in-on-line-discussions-and-linkedin-groups/
There is no history effect in FD-SOI. Regarding self-heating, IBM Device Chief Designer Ed Nowak addressed self-heating & SOI (he was talking about FinFET, but cites planar SOI) a few weeks ago. He said, "Self-heating in SOI FinFETs is very similar to that in planar SOI MOSFETs, and as such, the issues and solutions are well understood at a practical product-applications level. For digital circuits, self-heating is not a consideration, as the short-transient energy dissipated from a single transition is absorbed by the heat capacity of the device with a negligible temperature rise. For circuits in which duty factors are sufficiently high, well-established CAD techniques from planar SOI offer solutions. A narrow sliver of silicon connecting a bulk FinFET to the substrate does reduce the degree of self-heating, but similar CAD requirements in product design remain. Other aspects surrounding self-heating include effects on device and interconnect aging, and here again, the techniques practiced over several generations of planar SOI enable design capability to assure the required product reliability in the field."
Other major issues is circuit self heating.
This complicates design flow and IP block.
Self heating causes transistor speed and leakage to be different based on past switching history.
This is why Intel is using bulk finfet vs FDSOI or SOI finfet. Why I think Intel dropped FDSOI. Intel solved SOI heat by using bulk so heat all goes to bottom of wafer.
Very smart of Intel.
never mind - I clicked on the wrong link
"IBS has been in the business of modeling and analyzing the impact of technology choices for clients in the semiconductor and related industries for over 20 years. Our robust approach has stood the test of time, enabling us to predict the economic impact of such decisions with a high degree of accuracy."
Intel runs multiple fabs and I am sure they (Intel) have n internal group that studies/develops very detailed cost comparision models.
"The time to reach defect density-related yields with allowance impact of parametric yields is estimated to be 12 to 18 months for FD-SOI versus 24 to 36 months for FinFETs."
Do you think 24 to 36 months would apply to Intel?
what would happen to the results of the model in case you plug in a 12 to 18 months for bulk ?
My judgment is different but I I welcome your insight on these issues. On your points
(1) SEH and MEMC have no meaningful FDSOI wafer supply as we speak. They are only on "paper" SOI" suppliers. I think the market data suggest this as AMD still pays extra $500? per SOI wafer after 10 years of production since SEH and MEMC have no SOI capacity. That extra price is a non-starter for mobile market.
(2) Doing "hybridization zones" to solve the ESD and HV devices circuits issues adds process cost and yield issues. Etching off the thin Si and Oxide layer removes the isolation layer, Thus device to device isolation now requires a deep trench to be added back into the process flow into these "hybridization zones". A process nightmare. (My guess is Handel missed this point in his cost study).
Next on hybridization zones since regions were etched off my wafer so by definition my wafer is NOT planar (i.e. not flat) for gate patterning or for entire front-end lithography. Having a not planar front end is another non starter due to lithography tool depth of field and Gate patterning would be very poor leading to poor yield.
Lastly you did not comment on the issues on restrictions on multi -threshold voltages. Looks to me to be yet another non-starter.
FDSOI have been a device options for 10 years. I think these are the reasons.
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I am really curious about this cost comparision model
I don't believe there is no defined cost saving because you compare variable cost (SoC wafers) versus fixed cost due to additional capex required due to using bulk
I am curious about the assumptions in this model
@Mrchipguy -- I'd posit that FD does not in fact have the same issues as PD. re: cost - there are 3 wafer suppliers (Soitec, SEH, MEMC). Also suggest Handel Jones' piece cited in my previous comment (he's got FD-SOI die cost = 50 to 60% savings compared to bulk or FinFET). re: physical design -- for ESD etc, because the top Si and insulating layers are so thin, for those devices they just etch back to the bulk (this is the "hybridization zones") -- you can read a full explanation in a white paper by Giorgio Cesana et al from a year ago at http://www.soiconsortium.org/pdf/fullydepletedsoi/planar_fd_silicon_technology_competitive_soc_28nm.pdf. And what they're doing with biasing is awesome.
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