So industry is already thinking about 7nm ? How far we can shrink the transistor ? I think we are approaching the limit and soon companies will start building new architecture's to enhance the performance instead of worry about shrinking the transistor.
I am wondering if Samsung/Gloflo "roadmap" was backed up by a manufacturing/litho roadmap.
I clicked on the slides - one said 14nm on track...
I would imagine being a customer you would want to now what process you actually use before taping it out?
ASML mentioned that foundry process would require EUV @14nm - I am curious why TSMC selected 16nm FinFet as next generation following 20nm planar.
"It’s not clear how much chip designers will demand the 14 nm FinFET process which carries significant costs and marginal advantages over a coming 20 nm node."
Shouldn't they figure this out?
I get impression they just follow blindly Intel roadmap.
The 20 nm node is the first to require double patterning, a cost adder. The 14 nm node is essentially a 20 nm process with FinFETs, another cost, said IBM’s Patton.
That comes from an "IBMer" - makes me scratch my head -
imagine you are a potential customer and you evaluate TSMC, Gloflo and Samsung.
which one would you pick?
Fully depleted technologies like FDSOI and FinFET use undoped channels- so basically zero dopants, except for the source and drain. Of course there may be some doping of Fins for various reasons in the early implementations, but ultimately it will be undoped channels. And junctionless transistors have been demonstrated as well if you are worried about the S/D doping.
Oh and P.S. "everyone thought" 100nm was the limit at one time as well. I have yet to hear Intel, IBM, Samsung, TSMC or any IDM/Foundry say there is any hard limit in the foreseeable future. The limit will come from economics, not physics- it will just get too expensive to stay on Moore's law at some point.
Surprised the article didn't mention DSA prominently (directed self assembly)- they spent some time on that as well and that can reduce the need for double/triple/quadruple patterning as well. That is one area where IBM has made some real advances. But I don't recall seeing any litho roadmap slide- no.
And to their credit (contrary to your impression) they don't seem to be following blindly the Intel roadmap. K. Kuhn and M. Bohr have been touting tunnel FETs and Ge/III-V channels lately. IBM basically dismissed those solutions and said Si nanowire followed by carbon nanotubes is how they think it will go.
This would explain why TSMC sticks with 16nm rather 14nm.
I believe back in July during ASML CC ASML stated that foundries face additional challenge compared to IDM due to design rules / (aggressive) shrinkfactor and the conclusion from what I recall was that foundries would need EUV @14nm.
I believe they also stated that DRAM people would be first in adopting EUV.
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