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dimopep
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re: Stitch and ship will sink your chip every time
dimopep   2/17/2013 12:28:22 PM
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The complexity of todayís SoC simply doesnít allow for stitch & ship mentality. In fact verification teams nowadays spend much more time at the higher integration levels. This can be easily recognized in the numerous heterogeneous prototyping environment, e.g. virtual prototypes coupled with FPGA platforms, and the amount of testing performed prior and after tapeout. There certainly is a difference between consumer electronics and military, but every SoC team who wants to be successful has to obey the facts and schedule accordingly.

TomA Breker
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re: Stitch and ship will sink your chip every time
TomA Breker   2/15/2013 7:08:50 PM
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Many of our customers have horror stories to tell about previous SoC projects with silicon bugs that should have been caught before fabrication. Of course we can't share those stories and offer "proof" that there is a stitch-and-ship mentality at work. I would say that most verification engineers understand the risk this practice entails but are given neither the schedule nor the resources to do anything better.

resistion
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re: Stitch and ship will sink your chip every time
resistion   2/15/2013 6:11:42 PM
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Take a look at Qualcomm Snapdragon - they have been successful at sampling. Are they guilty of stitch and ship? Can we assume they did the system level checks, before sampling.

resistion
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re: Stitch and ship will sink your chip every time
resistion   2/15/2013 11:38:14 AM
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I guess I would like to see proof that there is widespread neglect of system level verification with the resulting dire consequences.

rkadam
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re: Stitch and ship will sink your chip every time
rkadam   2/15/2013 10:01:39 AM
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Excellent article, yes there is this stupid mentality that if the IP's are proven you can get a chip taped out in 2-3 months, without really giving thought on the integration. I feel that ASIC engineering has now become more system oriented which needs more system level thinking, as most of the blocks are available in some or the other form of RTL IP. But what is lacking is acceptance of the same, and lack of ASIC engineers understanding the systems. It is high time that software engineers work very closely with hardware engineers on SOC, for sure success.

resistion
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re: Stitch and ship will sink your chip every time
resistion   2/15/2013 2:57:17 AM
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There must be some full-chip simulation software out there today. Why would it not be used? Too expensive? Not yet fully developed or calibrated?

vapats
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re: Stitch and ship will sink your chip every time
vapats   2/14/2013 12:27:25 AM
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Thanks for this excellent and thoughtful article, Maheen; I hope that newcomers to our profession are paying attention. All too often, I see a "lego-block" mentality, that neglects the reality of total system integration... until sober reality bites you in the butt!

old account Frank Eory
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re: Stitch and ship will sink your chip every time
old account Frank Eory   2/13/2013 2:10:17 PM
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I sincerely hope that not many SoC teams are practicing stitch & ship. To say it is a recipe for disaster is stating the obvious. Every system requires system engineering and verification against clear requirements.

resistion
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re: Stitch and ship will sink your chip every time
resistion   2/12/2013 1:21:28 PM
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It's easy to discuss but hard to practice. Sometimes you'll only catch the most insidious things after it's been fabricated under the most reasonable assumptions and out in the field for some time. So the practice of sampling needs to be established.

Oneppm
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re: Stitch and ship will sink your chip every time
Oneppm   2/11/2013 4:49:07 PM
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This is a very timely article. I think that SOC development teams will be slower to embrace this than the emerging 3D/SIP development teams. To help the 3D movement, I recently embraced a new Conference being sponsored by the IPC, the IPC ESTC which has been created to help bring the bridges of knowledge from the chips to the systems closer together. Phil Marcoux

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