Excellent assessment. Chip people needs to look at the application. This is the mantra since the beginning of time. But it is getting more and more urgent. System integration in DoD is good example. It has been there because there is a single customer - DoD. They know exactly what they want. System integrators too, sort of, know what customer wants.
I think the chip industry needs to look beyond the chip engineering. End applications consist of multi-physics system. There need to be top-down engineering consisting of multi-disciplinary engineering, like DoD system development.
This is a very timely article. I think that SOC development teams will be slower to embrace this than the emerging 3D/SIP development teams.
To help the 3D movement, I recently embraced a new Conference being sponsored by the IPC, the IPC ESTC which has been created to help bring the bridges of knowledge from the chips to the systems closer together.
It's easy to discuss but hard to practice. Sometimes you'll only catch the most insidious things after it's been fabricated under the most reasonable assumptions and out in the field for some time. So the practice of sampling needs to be established.
I sincerely hope that not many SoC teams are practicing stitch & ship. To say it is a recipe for disaster is stating the obvious. Every system requires system engineering and verification against clear requirements.
Thanks for this excellent and thoughtful article, Maheen; I hope that newcomers to our profession are paying attention.
All too often, I see a "lego-block" mentality, that neglects the reality of total system integration... until sober reality bites you in the butt!
Excellent article, yes there is this stupid mentality that if the IP's are proven you can get a chip taped out in 2-3 months, without really giving thought on the integration. I feel that ASIC engineering has now become more system oriented which needs more system level thinking, as most of the blocks are available in some or the other form of RTL IP. But what is lacking is acceptance of the same, and lack of ASIC engineers understanding the systems.
It is high time that software engineers work very closely with hardware engineers on SOC, for sure success.
Many of our customers have horror stories to tell about previous SoC projects with silicon bugs that should have been caught before fabrication. Of course we can't share those stories and offer "proof" that there is a stitch-and-ship mentality at work. I would say that most verification engineers understand the risk this practice entails but are given neither the schedule nor the resources to do anything better.
Blog Doing Math in FPGAs Tom Burke 13 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...