This is a processor core tailored to the imaging pipeline.
Just as Tensilica used its software profiling tools to create an optimized CPU for its HiFi family of audio DSPs, Tensilica engineers, this time around, "created a specialized DSP with an instruction set that reduces the cycle count of the key embedded vision algorithms," according to Linley Group's Gardner.
Article completely left out CogniVue Corporation which was a founding member of EVA before CEVA and Tensilica announced their vision cores. CogniVue's APEX image cognition processor (ICP) technology addresses what is mentioned in this article as key - an efficient processor architecture for vision processing is not just about massively parallel pixel processing, but about creating vision friendly data structures, minimizing data movement and somehow achieving na efficiently pipelined implementation of very complex vision algorithms.
Actually there is a 3rd player in the mix in the form of CogniVue with their Image Cognition Processing (ICP) technology. CogniVue has been designing vision processing IP for low power embedded and mobile applications for several years and launched the ICP architecture in 2010, making the IP available in their own SOC. In 2012 CogniVue licensed their ICP APEX processing core to Freescale (http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1734693&highlight=) for vision processing in Automotive safety applications. CogniVue is now a technology licensing company squarely focused on embedded vision processing, and in fact was one of the founding members of the Embedded Vision Alliance in 2011. The comments in the article about the complexities of vision processing are quite accurate and the ICP APEX processing core is specifically architected to "hide" memory access latency while optimizing the vision processing pipeline. Check us out at www.cognivue.com.