I have seen both Gate 1st and gate last processes, what really matters is whether each tech can provide the published specs with reasonable yield, in time for customer shipment. Non-Intel fabs have had a hard time delivering Yield on time in HKMG ,primarily coz,it was their 1st time producing it in 32/28nm. Intel was already playing with it since 65nm days.,
It seems a bit early to be predicting what will happen at 7 nm, but if DSA continues to rapidly evolve then perhaps it can be a disruptive technology by then. If we are stuck with quad patterning I can't see it being cost effective.
An electron with 1.5 eV kinetic energy has 1 nm wavelength. If we keep on reducing voltages and dimensions we could have some quantum crossover, like at ~2 nm. If the dimensions are (already) less than the electron mean free path, then it gets really interesting.
HS seems to have an understanding of why IBM is still in semiconductors, mainly to support their systems business, and in that regard they are successful. It is a relatively small operation with one 200 mm and one 300 mm fab - running about 5 process nodes worth of tech under one roof v. Intel's many Fab high volume operation, why even make a comparison there ? Two different businesses. I am not a Phd like I imagine many of you commentators are, so can you please explain why you consider the gate first approach to be so inferior v. gate last ?
IBM Makes its money from Selling Enterprise Systems, that include full bundle including Software, Servers, data warehouse, and services. IBM Chip tech is developed for its server Chips and related SOCs, That gives them tech advantage over competition.
Blog Doing Math in FPGAs Tom Burke 18 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...