The Rayleigh resolution limit (k1=0.61) of ASML's EUV tool (NA=0.33) is 25 nm. So by the time they use for 7 nm, it would need the same OPC and enhancement tricks used for 193 nm immersion today. But EUV was originally justified as a way to avoid these tricks. In that sense, it has already failed its promise.
There are two competitive semiconductor technologies today: FD-FinFETs by Intel and FDSOI by IBM. Major difference is scalability. Based on the semiconductor device physics theory, the FDSOI channel thickness required to suppress transistor leakage current is 7nm for 22nm-node, 4nm for 14nm-node, 3nm for 10nm-node, and 2nm for 7nm-node. Meanwhile, for FD-FinFETs the fin width (equivalent to channel thickness) required is 22nm for 22nm-node, 14nm for 14nm-node, 10nm for 10nm-node, and 7nm for 7nm-node or fin width = gate length, Lg. What a large difference favoring FinFETs! For the 22nm-node FDSOI the channel thickness of 7nm is required while for 22nm FinFETs the fin width as large as 22nm is required to suppress transistor leakage current. That is why Intel’s 22nm FinFETs are in high Volume manufacturing for almost two years, and 14nm will be manufactured at 2014, but FDSOI at 22nm and below will not be manufacturable because Soitec can’t deliver such thin 7nm, 4nm, 3nm and 2nm FDSOI. What Soitec can deliver today is high volume manufacturing of 28nm SOI wafers with minimum 12nm SOI and 25nm buried oxide. FinFETs are not dependent on Soitec wafers.
IBM Patton predicts the next big thing after FinFETs will be carbon nanotubes. But he doesn’t say at what technology node FinFETs will end? Intel Mark Bohr said FinFETs can be extended to the end of scaling. I disagree with Mark. In my opinion it is plausible to manufacture the fin width equal to 7nm, but not below because of the quantum confinement induced device variability. The manufacturability of the 7nm carbon nanotube with possibly 3nm or less nanotube diameter has not been demonstrated yet. The other critical issues are self-heating, source/drain resistance and quantum confinement effects. Skim
These subwavelength optical confinement activities are related to plasmons. The surface plasmon polariton modes in metamaterials is the source of negative refraction. But plasmons have their own well-known limits.
I think that is the reason for the interest in silicon photonics. A group at Northwestern has made a bow-tie shaped 3D metamaterial nanocavity with a negative index of refraction and demonstrated a laser that defies the diffraction limit of light, emitting coherent IR wavelength light from a cavity structure that is much smaller than the wavelength. This shouldn't be possible either, but it is.
Sometimes we think we know, based on the best available science, only to find out later that the science wasn't quite right. Nano-photonics is at this stage, just now finding oddities in optical principles that have been considered sacrosanct since the 19th century.
If photonic chips can be built with the same CMOS process, and it looks like they can, then I think we will be using photons instead of electrons before 2 nm is reached. Yet there remains the possibility that the as of yet untested predictions are not quite accurate, so we won't know for certain where the quantum limit is until we can actually reach it and the theoretical physics versus experimental physics debates are settled.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.