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any1
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CEO
re: ISSCC: ASML says EUV best option at 10nm
any1   2/20/2013 1:24:53 AM
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EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?

Alex33
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re: ISSCC: ASML says EUV best option at 10nm
Alex33   2/19/2013 6:07:13 PM
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Not at metal1. Every node a few more restrictions creep in, but it is nothing close to unidirectional. You won't get enough pin placements in the std cells without allowing 2D designs.

kjdsfkjdshfkdshfvc
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Rookie
re: ISSCC: ASML says EUV best option at 10nm
kjdsfkjdshfkdshfvc   2/19/2013 2:34:39 PM
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Wow, I just learned me something. http://bit.ly/dI3hcF

resistion
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CEO
re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 1:30:56 PM
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"..no one uses wire bends anymore..." It's true, layouts would be almost entirely cut lines.

greenpattern
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re: ISSCC: ASML says EUV best option at 10nm
greenpattern   2/19/2013 11:37:37 AM
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The first slide showed power fluctuations of more than 10% - is that normal?

resistion
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CEO
re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 10:14:15 AM
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ASML promised 70 WPH @ 15 mJ/cm2, but what if that dose is not enough? What if need 60? They cannot ever be the cost-effective solution.

double-o-nothing
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Rookie
re: ISSCC: ASML says EUV best option at 10nm
double-o-nothing   2/19/2013 10:06:03 AM
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The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.

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