Breaking News
Comments
Oldest First | Newest First | Threaded View
Page 1 / 2   >   >>
double-o-nothing
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
double-o-nothing   2/19/2013 10:06:03 AM
NO RATINGS
The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.

resistion
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 10:14:15 AM
NO RATINGS
ASML promised 70 WPH @ 15 mJ/cm2, but what if that dose is not enough? What if need 60? They cannot ever be the cost-effective solution.

greenpattern
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
greenpattern   2/19/2013 11:37:37 AM
NO RATINGS
The first slide showed power fluctuations of more than 10% - is that normal?

resistion
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 1:30:56 PM
NO RATINGS
"..no one uses wire bends anymore..." It's true, layouts would be almost entirely cut lines.

kjdsfkjdshfkdshfvc
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
kjdsfkjdshfkdshfvc   2/19/2013 2:34:39 PM
NO RATINGS
Wow, I just learned me something. http://bit.ly/dI3hcF

Alex33
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
Alex33   2/19/2013 6:07:13 PM
NO RATINGS
Not at metal1. Every node a few more restrictions creep in, but it is nothing close to unidirectional. You won't get enough pin placements in the std cells without allowing 2D designs.

any1
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
any1   2/20/2013 1:24:53 AM
NO RATINGS
EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?

resistion
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
resistion   2/20/2013 1:58:18 AM
NO RATINGS
Bi-directional M1 is commonly practiced but not necessary. In fact, given EUV's inherent X-Y asymmetry, unidirectional will always be lithographically preferred.

InVT
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
InVT   2/20/2013 4:50:16 PM
NO RATINGS
I'm guessing if they develop a pellicle process they are going to have to bring it up well above 60W.

pica0
User Rank
Author
re: ISSCC: ASML says EUV best option at 10nm
pica0   2/21/2013 2:05:32 PM
NO RATINGS
Any energy consumption estimations?

Page 1 / 2   >   >>


Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)
Like Us on Facebook
Special Video Section
Protecting sensitive electronic circuitry from voltage ...
09:45
Watch as a web server authenticates or rejects a water ...
Protecting sensitive electronic circuitry from voltage ...
Watch as a web server authenticates or rejects a water ...
Protecting sensitive electronic circuitry from voltage ...
Power can be a gating factor in success or failure of ...
Get to market faster and connect your next product to the ...
00:44
See how microQSFP is setting a new standard for tomorrow’s ...
The LTC3649 step-down regulator combines key features of a ...
Once the base layer of a design has been taped out, making ...
In this short video we show an LED light demo to ...
The LTC2380-24 is a versatile 24-bit SAR ADC that combines ...
In this short video we show an LED light demo to ...
02:46
Wireless Power enables applications where it is difficult ...
07:41
LEDs are being used in current luxury model automotive ...
With design sizes expected to increase by 5X through 2020, ...
01:48
Linear Technology’s LT8330 and LT8331, two Low Quiescent ...
The quality and reliability of Mill-Max's two-piece ...
LED lighting is an important feature in today’s and future ...
05:27