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double-o-nothing
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re: ISSCC: ASML says EUV best option at 10nm
double-o-nothing   2/19/2013 10:06:03 AM
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The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 1:30:56 PM
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"..no one uses wire bends anymore..." It's true, layouts would be almost entirely cut lines.

Alex33
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re: ISSCC: ASML says EUV best option at 10nm
Alex33   2/19/2013 6:07:13 PM
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Not at metal1. Every node a few more restrictions creep in, but it is nothing close to unidirectional. You won't get enough pin placements in the std cells without allowing 2D designs.

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   2/20/2013 1:58:18 AM
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Bi-directional M1 is commonly practiced but not necessary. In fact, given EUV's inherent X-Y asymmetry, unidirectional will always be lithographically preferred.

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   2/19/2013 10:14:15 AM
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ASML promised 70 WPH @ 15 mJ/cm2, but what if that dose is not enough? What if need 60? They cannot ever be the cost-effective solution.

greenpattern
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re: ISSCC: ASML says EUV best option at 10nm
greenpattern   2/19/2013 11:37:37 AM
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The first slide showed power fluctuations of more than 10% - is that normal?

kjdsfkjdshfkdshfvc
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re: ISSCC: ASML says EUV best option at 10nm
kjdsfkjdshfkdshfvc   2/19/2013 2:34:39 PM
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Wow, I just learned me something. http://bit.ly/dI3hcF

any1
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re: ISSCC: ASML says EUV best option at 10nm
any1   2/20/2013 1:24:53 AM
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EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   2/26/2013 2:10:53 AM
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SPIE Keynote from Intel showed EUV out at 10 nm (still in pilot), with only 193 nm extension being used for production at 2H 2015.

InVT
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re: ISSCC: ASML says EUV best option at 10nm
InVT   2/20/2013 4:50:16 PM
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I'm guessing if they develop a pellicle process they are going to have to bring it up well above 60W.

pica0
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re: ISSCC: ASML says EUV best option at 10nm
pica0   2/21/2013 2:05:32 PM
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Any energy consumption estimations?

de_la_rosa
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re: ISSCC: ASML says EUV best option at 10nm
de_la_rosa   2/21/2013 4:21:15 PM
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I wonder if those resolution results are representative for high throughput conditions. They are flogging a dead horse!

Diogenes53
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re: ISSCC: ASML says EUV best option at 10nm
Diogenes53   2/22/2013 1:53:04 AM
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Bring on angstroms! The horse died when the name was changed from soft x-ray projection lithography to EUV. Who says words don't matter.

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   2/23/2013 10:26:30 PM
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Why did they present this at ISSCC? The conference is about circuits and designs, not about devices and processes, don't even mention lithography!

double-o-nothing
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re: ISSCC: ASML says EUV best option at 10nm
double-o-nothing   2/24/2013 1:24:48 AM
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SPIE Advanced Lithography this week is where the updates on lithography happen.

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   6/13/2013 5:02:45 AM
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The SPIE material is publicly available: http://www.asml.com/doclib/investor/presentations/2013/asml_20130228_EUV_presentation_SPIE_public.pdf

resistion
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re: ISSCC: ASML says EUV best option at 10nm
resistion   6/13/2013 5:24:54 AM
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The 2D feature resolution is still not beating 22 nm and roughness about 15% of that. Photon shot noise is not negligible anymore.



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