The 18 nm hp holes show large non-uniformity and the 13 nm hp lines much roughness. The end result is not just ASML's optics, it's also the resist and the mask blank defects. It's also interesting they still need multiple patterning to extend EUV's usability. Also, I'm pretty sure no one uses wire bends anymore at such small scales.
EUV missed insertion at 14 nm for Intel and I've heard before that Intel thinks 10nm is possible without EUV. Where does that leave TSMC, GLOFO, and Samsung? Will Intel gap them by another node before EUV is ready?