SOITEC provides 12nm wafers because they are asked to. It's not that they are limited to 12nm and manufacturers have to take the extra burden of thinning the wafer to the desired thickness. You need a few nm as a part of STI formation (so-called padox) and a few nm for thick oxide devices and HK gate pre-clean. All these steps are precise oxidation steps that have been used in in the industry for many years to form the gate oxide (which has been by far the most uniform process step in ic manufacturing).
IBM invented PDSOI, FDSOI, and E (extremely)T (thin) SOI technologies over twenty years of time period. PDSOI was very successful products. IBM and its SOI Consortium have spent enormous resources and efforts for volume manufacture of FDSOI and ETSOI including UTBB, but have not been successful. No FDSOI is manufactured at any node even today or the 22nm era. The major reason is for the 28 node a 7nm and for 22nm node 5.5nm extremely thin channel ETSOI are required to suppress the transistor leakage current or short channel effects. However, such ultra-thin 7nm and 5.5 nm ETSOI can’t be manufactured by Soitec. What Soitec can deliver today is 28nm SOI wafers with minimum channel thickness of 12nm and 25nm buried oxide. Therefore, STM’s repeated claims to have advantages over planar bulk CMOS and FinFETs in performance, power consumption and manufacturability are not justified because the 28nm planar bulk is in high volume manufacturing over 3 years and Intel’s FinFETs are also in high volume manufacturing for almost 2 years, but STM’s FDSOI is not manufactured yet and not likely.
STM’s 28nm wafer process sounds like etching back 5nm silicon from the 12nm silicon film to obtain a final 7nm. My question is such an extremely thin 5nm silicon can be etched back to obtain a final 7nm uniformly and reliably across the 300mm wafer in volume manufacturing. It sounds like a test chip or test wafer process. The published 7nm and 6nm data is test chip or test wafer data. STM claims it is qualified for production.