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KRS03
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re: NXP adds silicon 'fingerprint' to SmartMX2 MCUs
KRS03   2/23/2013 3:54:14 AM
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I'm sure that "a series of metastable SRAM bits" is oversimplifying the design significantly. The ID must not change over the lifetime of the part and over a variety of power-up conditions and temperatures.

daleste
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re: NXP adds silicon 'fingerprint' to SmartMX2 MCUs
daleste   2/23/2013 10:01:31 PM
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I agree. They would have to have a lot of bits and some algorithm that would check that is is close to the original pattern.

krisi
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re: NXP adds silicon 'fingerprint' to SmartMX2 MCUs
krisi   2/25/2013 5:02:16 PM
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Cool technology...I am not sure I understand KRS03 how the power up sequence can change in a lifetime of the product...presumably there is a recommended sequence for this and chip controls it to some extent too

Wung
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re: NXP adds silicon 'fingerprint' to SmartMX2 MCUs
Wung   2/25/2013 5:48:27 PM
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Is this a kind of SRAM-based hardware CAM IC design?



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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