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Koda23
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re: FPGAs add comms cores amid ASIC debate
Koda23   3/14/2013 11:27:14 PM
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It's also interesting to see the number of partner and 3rd party cores in the portfolios from Xilinx and Altera. My company often uses a mix of cores from 3rd parties and the FPGA manufacturer, depending on technical characteristics, availability, reliability, and cost. Our products are also high performance, low volume using lots of FPGAs and very few (if any) ASICs.

daleste
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re: FPGAs add comms cores amid ASIC debate
daleste   3/13/2013 1:47:08 AM
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It is more expensive to develop an ASIC at the next node. You have to have a big volume to justify the expense. FPGAs are more expensive per unit, but the development cost can be less. It is not free, but at least you can make software changes.

sridhar.ps
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re: FPGAs add comms cores amid ASIC debate
sridhar.ps   3/13/2013 12:35:29 AM
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All these market data quote development cost of ASICs, but there is sizeable design, verification and implementation costs on FPGAs as well. The data should highlight the difference in costs between FPGA based and ASIC based development, not just the cost of an ASIC development project.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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