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electrotechnics
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re: ST linked to Indian wafer fab bid
electrotechnics   3/25/2013 6:08:30 AM
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This is an ambitious project that will elevate india to a greater height should it succeed . i will be keen on the project as iam also interested in chip design

escher
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re: ST linked to Indian wafer fab bid
escher   3/25/2013 2:07:27 AM
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Yet another project doomed to failure - can India succeed in chip manufacturing when solar cell and module makers struggle with poor infrastructure, lack of trained staff and stifling export/import regulations?

chipmonk0
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re: ST linked to Indian wafer fab bid
chipmonk0   3/22/2013 5:05:02 PM
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Looks like these people in India know nothing ( or do not want to learn ) about the strategies followed by Taiwan, So. Korea, Singapore etc. Those countries did not jump from rice fields into Fabs at the latest node ( or even 3 nodes old e,g. 130 nm ) but accepted a sane & realistic learning curve - started with assembly,chip packaging, making simpler components and so on till they had both the trained manpower and credibility to embark on old - node Fabs. Even then it took the best of those Fabs ( eg. TSMC ) a full decade to catch up with the latest node. Even if this HSMC Co. in India gets 2 node old 45 nm technology from ST or Tower how long will it take them to get their act together and manage repectable yield and then gather up the guts to go on to 32, 28 nm ...? Do they have enough Capital to burn for the 10 years or longer it has taken others to climb that Hill ? Its obvious -- they need some good advice & execution



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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