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electrotechnics
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re: ST linked to Indian wafer fab bid
electrotechnics   3/25/2013 6:08:30 AM
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This is an ambitious project that will elevate india to a greater height should it succeed . i will be keen on the project as iam also interested in chip design

escher
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re: ST linked to Indian wafer fab bid
escher   3/25/2013 2:07:27 AM
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Yet another project doomed to failure - can India succeed in chip manufacturing when solar cell and module makers struggle with poor infrastructure, lack of trained staff and stifling export/import regulations?

chipmonk0
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re: ST linked to Indian wafer fab bid
chipmonk0   3/22/2013 5:05:02 PM
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Looks like these people in India know nothing ( or do not want to learn ) about the strategies followed by Taiwan, So. Korea, Singapore etc. Those countries did not jump from rice fields into Fabs at the latest node ( or even 3 nodes old e,g. 130 nm ) but accepted a sane & realistic learning curve - started with assembly,chip packaging, making simpler components and so on till they had both the trained manpower and credibility to embark on old - node Fabs. Even then it took the best of those Fabs ( eg. TSMC ) a full decade to catch up with the latest node. Even if this HSMC Co. in India gets 2 node old 45 nm technology from ST or Tower how long will it take them to get their act together and manage repectable yield and then gather up the guts to go on to 32, 28 nm ...? Do they have enough Capital to burn for the 10 years or longer it has taken others to climb that Hill ? Its obvious -- they need some good advice & execution



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michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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