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re: Tech Beat: Nano-structures promise power-sipping PCM
resistion   3/22/2013 8:47:17 AM
A big problem with this is reducing the contact area increases the voltage from larger contact resistance. Also, isn't it standard practice to have design one self-assembled contact hole inside the TiN contact?

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re: Tech Beat: Nano-structures promise power-sipping PCM
green_is_now   3/22/2013 2:25:37 AM
This will also lower contact area

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re: Tech Beat: Nano-structures promise power-sipping PCM
green_is_now   3/22/2013 2:25:07 AM
Why not etch away area instead or in combination with this technque?

R G.Neale
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re: Tech Beat: Nano-structures promise power-sipping PCM
R G.Neale   3/20/2013 1:23:25 PM
A correction and an apology. My quote of current densities of the order 10E8 amps/sq-cm reproduced above was based on my estimate for a sub 20nm device and the reading of a less than clear version of the original paper. I have been in contact with the authors who have drawn my attention to the supplementary information provided with their paper. From their simulation of a 50 x 50 nm device the current density without the oxide balls is 1.8 x 10E7 A/sq-cm; which is in good agreement with similar sized devices reported elsewhere. More importantly, and again from their simulation, with the oxide balls covering 50% of the area between the GST-TiN heater interface the authors estimate a reset current density of 2.8 x10E6 A/sq-cm. A value that betters by about an order of magnitude any reported so far by any other PCM workers for devices of similar dimensions. Assuming those operating conditions produce reliable overall performance especially with respect to elevated temperature data retention and write/erase lifetime the KAIST paper might mark a significant step forward in PCM development. The next, and non-trivial step, is reduction to practice with real devices and then to put PCM back into a competitive position, devices scaled to sub 20nm dimensions. For PCM the curve of reset current density J = f(dimensions) follow the general form of those for the ratio of surface area to volume. This would suggest that sub 20nm PCM devices without the oxide balls would have current densities close to 1x10E8 amps and given a similar gain reported above with the inclusion of the balls would result in a device with a reset current density of the order 1 x10E7 A/sq-cm. Much depends on the minimum possible diameter balls and the ability to reproduce very small diameter oxide balls in sub 20nm apertures. A significant challenge remains.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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